SW2
ON
1 2 3 4 5 6
Interrupt Status Register
SW2
ON
1 2 3 4 5 6
Scratchpad Register
Slide position 6 of SW2 toward the top of the
interrupt status register, or toward the bottom of the
Figure 7 --- Enabling the Interrupt Status Register
When a hardware interrupt occurs, reading the interrupt status register will return the interrupt status of the entire ES-100D, as shown in Figure 8. Individual bits are cleared as the interrupting ports are serviced. The interrupt service routine must ensure that the interrupt status register reads zero before exiting, or the ES-100D will be unable to signal subsequent interrupts.
An I/O write to the interrupt status register will cause another hardware interrupt to be generated if the interrupt status register is non-zero. The value written is ignored and has no effect on the contents of the interrupt status register.
BIT | DESCRIPTION |
7 (MSB) | 1 if interrupt pending on Serial 8 |
|
|
6 | 1 if interrupt pending on Serial 7 |
|
|
5 | 1 if interrupt pending on Serial 6 |
|
|
4 | 1 if interrupt pending on Serial 5 |
|
|
3 | 1 if interrupt pending on Serial 4 |
2 | 1 if interrupt pending on Serial 3 |
|
|
1 | 1 if interrupt pending on Serial 2 |
|
|
0 | 1 if interrupt pending on Serial 1 |
|
|
Figure 8 --- Interrupt Status Register contents
Quatech | 7 |
