M65881AFP
PIN DESCRIPTION
Pin No. | Name | I/O | Description |
1 | VddL |
| Power Supply for Lch PWM Power Stage (3.3V) |
2 | OUTL1 | O | Lch PWM1 Output for Power Stage |
3 | VssL |
| GND for Lch PWM Power Stage |
4 | OUTL2 | O | Lch PWM2 Output for Power Stage |
5 | XOVdd |
| Power Supply for Secondary Master Clock Buffer ( 3.3V ) |
6 | XfsoOUT | O | Buffered Output of Secondary Master Clock (1024/512fso) |
7 | XOVss |
| GND for Secondary Master Clock Buffer |
8 | DVdd |
| Power Supply for Digital Block (1.8V) |
9 | DVss |
| GND for Digital Block |
10 | MCKSEL | I | Secondary Master Clock Selector "L":1024fso, "H":512fso |
11 | SCDT | I | Serial Control • Data Input |
12 | SCSHIFT | I | Serial Control • Shift Clock Input |
13 | SCLATCH | I | Serial Control • Latch Signal Input |
14 | NSPMUTE | I | PWM Duty 50% Mute ( "L": Active ) |
15 | INIT | I | Initialize Input ( Power Supply Reset ) ; "L" : Reset, "H" : Release |
16 | LRCK | I | LRCK Input (PCM Signal ) |
17 | BCK | I | BCK Input ( PCM Signal ) |
18 | DATA | I | DATA Input ( PCM Signal ) |
19 | BFVdd |
| Power Supply for Input/Output 3.3V Buffer |
20 | BFVss |
| GND for Input/Output 3.3V Buffer |
21 | XfsiIN | I | Primary Master Clock Input (256fsi/512fsi ) |
22 | FsoCKO | O | Secondary Fso Clock Output |
23 | FsoI | I | Secondary Fso Clock Input |
24 | SFLAG | O | Asynchronous Flag ( H: Active ) |
25 | TEST2 | I | Test2 must be connected to GND |
26 | TEST1 | I | Test1 must be connected to GND |
27 | HPOUTR2 | O | Rch PWM2 Output for Headphone |
28 | HPVssR |
| GND for Rch Headphone |
29 | HPOUTR1 | O | Rch PWM1 Output for Headphone |
30 | HPVddR |
| Power Supply for Rch Headphone ( 3.3V ) |
31 | HPOUTL2 | O | Lch PWM2 Output for Headphone |
32 | HPVssL |
| GND for Lch Headphone |
33 | HPOUTL1 | O | Lch PWM1 Output for Headphone |
34 | HPVddL |
| Power Supply for Lch Headphone ( 3.3V ) |
35 | XVss |
| GND for Secondary Master Clock Input Buffer |
36 | XfsoIN | I | Secondary Master Clock Input (1024fso/512fso) |
37 | XVdd |
| Power Supply for Secondary Master Clock Buffer ( 3.3V ) |
38 | VssLR |
| GND for PWM Power Stage |
39 | OUTR2 | O | Rch PWM 2 Output for Power Stage |
40 | VssR |
| GND for Rch PWM Power Stage |
41 | OUTR1 | O | Rch PWM 1 Output for Power Stage |
42 | VddR |
| Power Supply for Rch PWM Power Stage ( 3.3V) |
Output |
|
Current |
|
on 3.3V | Signal Level |
– | – |
| 3.3V |
– | – |
| 3.3V |
– | – |
2mA | 3.3V |
– | – |
– | – |
– | – |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | 3.3V |
– | – |
– | – |
– | 3.3V |
4mA | 3.3V |
– | 3.3V |
4mA | 3.3V |
– | 3.3V |
– | 3.3V |
| 3.3V |
– | – |
| 3.3V |
– | – |
| 3.3V |
– | – |
| 3.3V |
– | – |
– | – |
– | 3.3V |
– | – |
– | – |
| 3.3V |
– | – |
| 3.3V |
– | – |
|
Rev.1.00 2003.05.08 | page 6 of 23 |
