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Samsung M471B1G73AH0 specifications Datasheet

Models: M471B1G73AH0

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Page 18

Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

NOTE :

1)Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2)Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3)Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4)Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5)Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6)Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7)IDD current measure method and detail patterns are described on DDR3 component datasheet

8)VDD and VDDQ are merged on module PCB.

9)DIMM IDD SPEC is measured with Qoff condition (IDDQ values are not considered)

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Samsung M471B1G73AH0 specifications Datasheet

Contents

Datasheet Rev HistoryFirst Release Jul Kim Table Of Contents Key Features Address ConfigurationDDR3 Unbuffered Sodimm Ordering Information X64 Dimm Pin Configurations Front side/Back Side Pin Front BackPin Description Pin Name Description NumberSymbol Type Function Input/Output Functional DescriptionFunction Block Diagram 8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMsAC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings10.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsSymbol Parameter DDR3-800/1066/1333/1600 Unit AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition +0.2Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Parameter DDR3-800/1066/1333/1600 Unit Min MaxDifferential AC and DC Output Levels AC & DC Output Measurement LevelsSingle Ended AC and DC Output Levels Single-ended Output Slew RateDelta TRdiff Differential output slew rate for falling edge Differential Output Slew RateDifferential output slew rate for rising edge Delta TFdiffDimm IDD specification definition Symbol DescriptionDatasheet IDD Spec Table M471B1G73AH0 8GB 1Gx64 ModuleM471B1G73AH0 Parameter Input/Output Capacitance14.1 2Rx8 2GB Sodimm DDR3-1066 DDR3-1333Electrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 Speed Bins DDR3-1333 CL-nRCD-nRPDDR3-1600 Speed Bins CL-nRCD-nRP Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075 Speed Bin Table NotesTiming Parameters by Speed Grade Timing Parameters by Speed BinReset Timing MIN MAX Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftrateX 1 + 0.15 x 15 = 0.133 ~~ 128ms Physical Dimensions 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0