Samsung S3C2440A CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Description Reset Value , CLKSLOW Bit Description Initial State

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT
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CLOCK SLOW CONTROL (CLKSLOW) REGISTER
Register Address R/W Description Reset Value
CLKSLOW 0x4C000010 R/W Slow clock control register 0x00000004
CLKSLOW Bit Description Initial State
UCLK_ON [7] 0: UCLK ON (UPLL is also turned on and the UPLL lock time is
inserted automatically.)
1: UCLK OFF (UPLL is also turned off.)
0
Reserved [6] Reserved –
MPLL_OFF [5] 0: Turn on PLL.
After PLL stabilization time (minimum 300us), SLOW _BIT
can be cleared to 0.
1: Turn off PLL.
PLL is turned off only when SLOW_BIT is 1.
0
SLOW_BIT [4] 0 : FCLK = Mpll (MPLL output)
1: SLOW mode
FCLK = input clock/(2xSLOW_VAL), when SLOW_VAL>0
FCLK = input clock, when SLOW_VAL=0.
Input clock = XTIpll or EXTCLK
0
Reserved [3] – –
SLOW_VAL [2:0] The divider value for the slow clock when SLOW_BIT is on. 0x4