Samsung S3C2440A - page 477

S3C2440A RISC MICROPROCESSOR SPI

22-7

SPI STATUS REGISTER

Register Address R/W Description Reset Value

SPSTA0 0x59000004 R SPI channel 0 status register 0x01

SPSTA1 0x59000024 R SPI channel 1 status register 0x01

SPSTAn Bit Description Initial State

Reserved [7:3]

Data Collision

Error Flag (DCOL)

[2] This flag is set if the SPTDATn is written or SPRDATn is read while

a transfer is in progress and cleared by reading the SPSTAn.

0 = not detect 1 = collision error detect

0

Multi Master Error

Flag (MULF)

[1] T his flag is set if the nSS signal goes to active low while the SPI is

configured as a master, and SPPINn's ENMUL bit is multi master

error detect mode. MULF is cleared by reading SPSTAn.

0 = not detect 1 = multi master error detect

0

Transfer Ready

Flag (REDY)

[0] This bit indicates that SPTDATn or SPRDAT n is ready to transmit

or receive. This flag is automatically cleared by writing data to

SPTDATn.

0 = not ready 1 = data Tx/Rx ready

1

SPI PIN CONTROL REGISTER

When the SPI system is enabled, the direction of pins except nSS pin is controlled by MSTR bit of SPCONn

register. The direction of nSS pin is always input.

When the SPI is a master, nSS pin is used to check m ulti-master error, provided that the SPPIN's ENMUL bit is

active, and another GPIO should be used to select a slave.

If the SPI is configured as a slave, the nSS pin is used to select SPI as a slave by one master.

Register Address R/W Description Reset Value

SPPIN0 0x59000008 R/W SPI channel 0 pin control register 0x00

SPPIN1 0x59000028 R/W SPI channel 1 pin control register 0x00

SPPINn Bit Description Initial State

Reserved [7:3]

Multi Master error

detect Enable

(ENMUL)

[2] The nSS pin is used as an input to detect multi master error when

the SPI system is a master.

0 = disable (general purpose) 1 = multi master error detect enable

0

Reserved [1] Reserved 0

Master Out Keep

(KEEP)

[0] Determine MOSI drive or release when 1byte transmit is completed

(master only).

0 = release 1 = drive the previous level

0

Contents

Main S3C2440A USER'S MANUAL 1 INTRODUCTION Page Page FEATURES (Continued) S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-5 ARM920T Bridge & DMA (4Ch) A H U S A P U S Figure 1-1. S3C2440A Block Diagram PIN ASSIGNMENTS Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 2 Page Page ARM State General Registers and Program Counter ARM State Program Status Registers Figure 2-3. Register Organization in ARM State THUMB State General Registers and Program Counter THUMB State Program Status Registers Figure 2-4. Register Organization in THUMB state Page Page Page Page Page Page Page Page Page Page Page 3 INSTRUCTION SET SUMMAY Figure 3-1. ARM Instruction Set Format Page Page THE CONDITION FIELD BRANCH AND EXCHANGE (BX) [3:0] Operand Register [31:28] Condition Field Page BRANCH AND BRANCH WITH LINK (B, BL) [24] Link bit [31:28] Condition Field Page DATA PROCESSING [11:0] Operand 2 type selection [15:12] Destination register [19:16] 1st operand register [20] Set condition codes Page Page [6:5] Shift type [11:7] Shift amount [6:5] Shift type [11:8] Shift register Page Page Page Page Page PSR TRANSFER (MRS, MSR) Figure 3-11. PSR Transfer Page Page MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) [15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code [31:28] Condition Field [21] Accumulate Page Page MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) [11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Set Condition Code [31:28] Condition Field [21] Accumulate [22] Unsigned Page Page SINGLE DATA TRANSFER (LDR, STR) Page Page Page Page Page HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) Page Page Page Page Page BLOCK DATA TRANSFER (LDM, STM) [19:16] Base Register [20] Load/Store Bit [21] Write-back Bit [22] PSR & Force User Bit [23] Up/Down Bit Page Figure 3-20. Pre-Increment Addressing Figure 3-21. Post-Decrement Addressing Page Page Page Page SINGLE DATA SWAP (SWP) [3:0] Source Register [15:12] Destination Register [19:16] Base Register [31:28] Condition Field [22] Byte/Word Bit Page SOFTWARE INTERRUPT (SWI) Page COPROCESSOR DATA OPERATIONS (CDP) Page COPROCESSOR DATA TRANSFERS (LDC, STC) Page Page Page Page Page Page Page Page Page Page Page 4 THUMB INSTRUCTION SET FORMAT FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. Figure 4-1. THUMB Instruction Set Formats Page Page FORMAT 1: MOVE SHIFTED REGISTER [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode Page FORMAT 2: ADD/SUBTRACT [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode [10] Immediate Flag Page FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode Page FORMAT 4 : ALU OP ERATIO NS [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Page FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Page Page FORMAT 6: PC-RELATIVE LOAD [7:0] Immediate Value Page FORMAT 7: LOAD/STORE WITH REGISTER OFFSET Page FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [11] H Flag [8:6] Offset Register [10] Sign-Extended Flag Page FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET Page FORMAT 10: LOAD/STORE HALFWORD [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag Page FORMAT 11: SP-RELATIVE LOAD/STORE [7:0] Immediate Value [11] Load/Store Bit Page FORMAT 12: LOAD ADDRESS [7:0] 8-bit Unsigned Constant [11] Source Page FORMAT 13: ADD OFFSET TO STACK POINTER [6:0] 7-bit Immediate Value [7] Sign Flag FORMAT 14: PUSH/POP REGISTERS [7:0] Register List [8] PC/LR Bit [11] Load/Store Bit Page FORMAT 15: MULTIPLE LOAD/STORE [7:0] Register List [10:8] Base Register [11] Load/Store Bit Page Page FORMAT 17: SOFTWARE INTERRUPT [7:0] Comment Field FORMAT 18: UNCONDITIONAL BRANCH [10:0] Immediate Value FORMAT 19: LONG BRANCH WITH LINK [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit Page INSTRUCTION SET EXAMPLES Page Page Page Page 5 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR Note: SROM means ROM or SRAM type memory 5-2 } Note Bank 6 and 7 must have the same memory size. FUNCTION DESCRIPTION Page Page S3C2440A RISC MICROPROCESSOR MEM ORY CONTROLLER DEC.13, 2002 5-7 ROM Memory Interface Examples Figure 5-4. Memory Interface with 8-bit ROM Figure 5-5. Memory Interface with 8-bit ROM x 2 5-8 Figure 5-6. Memory Interface with 8-bit ROM x 4 Figure 5-7. Memory Interface with 16-bit ROM S3C2440A RISC MICROPROCESSOR MEM ORY CONTROLLER DEC.13, 2002 5-9 SRAM Memory Interface Examples Figure 5-8. Memory Interface with 16-bit SRAM Figure 5-9. Memory Interface with 16-bit SRAM x 2 5-10 SDRAM Memory Interface Examples Figure 5-10. Memory Interface with 16-bit SDRAM (4Mx16, 4banks) Figure 5-11. Memory Interface with 16-bit SDRAM (4Mx16x4Bank * 2ea) Note Refer to Table 5-2 for the Bank Address configurations of SDRAM. DEC.13, 2002 PROGRAMMABLE ACCESS CYCLE Figure 5-12. S3C2440A nGCS Timing Diagram Figure 5-13. S3C2440A SDRAM Timing Diagram Page Page Page Page Page Page Page Page 6 Page Page Page SOFTWARE MODE Page Page Page 6-9 NAND FLASH MEMORY MAPPING Figure 6-4. NAND Flash Memory Mapping Note SROM means ROM or SRAM type memory NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-10 NAND FLASH MEMORY CONFIGURATION Figure 6-2 Two 8-bit NAND Flash Memory Interface Figure 6-3 A 16-bit NAND Flash Memory Interface Nand Flash configuration Register Page Page Page Page Page Page Page Page Page Page Page 7 FUNCTIONAL DESCRIPTION S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-3 Figure 7-1. Clock Generator Block Diagram Page Figure 7-2. PLL (Phase-Locked Loop) Block Diagram Figure 7-3. Main Oscillator Circuit Examples Page Page Page Page Power Management Figure 7-7. The Clock Distribution Block Diagram Page NORMAL Mode IDLE Mode SLOW Mode (Non-PLL Mode) Figure 7-9. Issuing Exit_from_Slow_mode Command in PLL on State Figure 7-10. Issuing Exit_from_Slow_mode Command After Lock Time Figure 7-11. Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously SLEEP Mode Follow the Procedure to Enter SLEEP mode Caution: Follow the Procedure to Wake-up from SLEEP mode Table 7-4. Pin configuration table in Sleep mode Pin Condition Guid of Pin Configuration Power Control of VDDi and VDDiarm NOTE S3C2440X Figure 7-12. SLEEP Mode NOTE Signaling EINT[15:0] for Wakeup Entering IDLE Mode PLL On/Off Pull-up Resistors on the Data Bus and SLEEP Mode Output Port State and SLEEP Mode Battery Fault Signal (nBATT_FLT) ADC Power Down CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register Address R/W Description Reset Value LOCKTIME Bit Descriptio n Initial Stat e MPLL Control Register UPLL Control Register PLL CONTROL REGISTER (MPLLCON & UPLLCON) Register Address R/W Description Reset Value PLLCON Bit Description Initial State PLL VALUE SELECTION TABLE Input Frequency Output Frequency MDIV PDIV SDIV CLOCK CONTROL REGISTER (CLKCON) Register Address R/W Description Reset Value CLKCON Bit Description Initial State CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Description Reset Value CLKSLOW Bit Description Initial State CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address R/W Description Reset Value CLKDIVN Bit Description Initial State CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER Register Address R/W Description Reset Value CAMDIVN Bit Descriptio n Initial Stat e 8 DMA REQUEST SOURCES DMA OPER ATION Page Page Transfer Size EXAMPLES DMA SPECIAL REGISTERS Page Page Page Page Page Page Page 9 Page Page Page Page Page PORT CONTROL DESCRIPTIONS I/O PORT CONTROL REGISTER Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page DCLKnDIV + 1 DCLKnCMP + 1 Page Page Page Page Page Page Page Page Page Page Page Page 10 PWM TIMER S3C2440A RISC MICROPROCESSOR 10-2 5:1 MUX 5:1 MUX Figure 10-1. 16-bit PWM Timer Block Diagram PWM TIMER OPERATION Command Status Page Page Page Page Page Page Page PWM TIMER CONTROL REGISTERS Page Page Page Page Page Page Page Page Page 11 UART S3C2440A RISC MICROPROCESSOR 11-2 Figure 11-1 UART Block Diagram (with FIFO) Page Page Page Page Page Page Page UART SPECIAL REGISTERS Page Page Page Page Page Page Page Page Page Page Page Page S3C2440A RISC MICROPROCESSOR USB HOST 12-1 12 HCM_ADR/ DATA(32) Figure 12-1. USB Host Controller Block Diagram USB HOST CONTROLLER SPECIAL REGISTERS 13 Page USB DEVICE CONTROLLER SPECIAL REGISTERS Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 14 Page Page Page Figure 14-2. Priority Generating Block Page INTERRUPT CONTROLLER SPECIAL REGISTERS Page Page Page Page Page Page Page Page Page Page Page 15 Page Page STN LCD CONTROLLER OPERATION Page Page Page Page Page Page Page LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-12 Figure 15-2. Monochrome Display Types (STN) Page Page Full Frame Timing(MMODE = 1, MVAL=0x2) Full Frame Timing(MMODE = 0) Figure 15-4. 8-bit Single Scan Display Type STN LCD Timing TFT LCD CONTROLLER OPERATION Page ...... Page Page Page Page Figure 15-6. TFT LCD Timing Example Page S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-25 Figure 15-7. Example of Scrolling in Virtual Display (Single Scan) Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 16 Page FUNCTION DESCRIPTIONS XP YP ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS Page Page Page Page Page 17 Page Page REAL TIME CLOCK SPECIAL REGISTERS Page Page Page Page Page Page 18 Page WATCHDOG TIMER SPECIAL REGISTERS Page 19 SD OPERATION SDIO OPERATION SDI SPECIAL REGISTERS Page Page Page Page Page Page Page Page 20 Page Page Figure 20-3. IIC-Bus Interface Data Format Page Page Page Page Page Page IIC-BUS INTERFACE SPECIAL REGISTERS Page Page Page 21 BLOCK DIAGRAM FUNCTIONAL DESCRIPTIONS AUDIO SERIAL INTERFACE FORMAT Page IIS-BUS INTERFACE SPECIAL REGISTERS Page Page Page 22 BLOCK DIAGRAM PCLK Pin Control Logic 0 APB I/F 0 Pin Control Logic 1 APB I/F 1 PCLK SPI OPERATION SPI S3C2440A RISC MICROPROCESSOR 22-4 Figure 22-2 SPI Transfer Format Page SPI SPECIAL REGISTERS Page Page 23 AHB bus S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-3 TIMING DIAGRAM Figure 23-2 ITU-R BT 601 Input Timing Diagram Page CAMERA INTERFACE OPERATION CAMIF External Camera Processor S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE mal-functioning External MCLK /d MPLL CAMPCLK Page S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE cGmGjGzGe cGmGjGzGecGmGjGzGe cGuGGGGGe cGmGjGzGe Page CAMERA INTERFACE SPECIAL REGISTERS Page Page Page Page Page Page Page Page Page Page Page Page Page Page 24 AC97 CONTROLLER OPERATION Page OPERATION FLOW CHART AC-LINK DIGITAL INTERFACE PROTOCOL AC97 POWERDOWN Page AC97 CONTROLLER SPECIAL REGISTERS Page Page Page Page 25 Page S3C2440A RISC MICROPROCESSOR MECHANICAL DATA 26-1 26 SAMSUNG Figure 26-1 289-FBGA-1414 Package Dimension 1 (Top View) MECHANICAL DATA S3C2440A RISC MICROPROCESSOR 26-2 27 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS D.C. ELECTRICAL CHARACTERISTICS Page Page Page Page Page S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-9 A.C. ELECTRICAL CHARACTERISTICS Figure 27-2 XTIpll Clock Timing Diagram Figure 27-3 EXTCLK Clock Input Timing Diagram HCLK (internal) EXTCLK t Page S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-11 Figure 27-7 Power-On Oscillation Setting Timing Diagram ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-12 Figure 27-8 Sleep Mode Return Oscillation Setting Timing Diagram S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-13 Page S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-15 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-16 S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-17 Figure 27-14 ROM/SRAM WRITE Timing Diagram (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-19 Page Figure 27-18 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11) ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-22 Figure 27-20 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit) S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-23 Figure 27-21 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2) ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-24 Figure 27-22 SDRAM MRS Timing Diagram S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-25 Figure 27-23 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-26 Figure 27-24 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3) S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-27 Figure 27-25 SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4) ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-28 Figure 27-26 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2) S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-29 Figure 27-27 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) Figure 27-28. SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) Figure 27-29. SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2) ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-32 Figure 27-30. External DMA Timing Diagram (Handshake, Single transfer) Figure 27-31. TFT LCD Controller Timing Diagram Page Page Figure 27-36. NAND Flash Address/Command Timing Diagram Figure 27-37. NAND Flash Timing Diagram