Samsung S3C2440A - page 325

S3C2440A RISC MICROPROCESSOR UART
11-21
UART BAUD RATE DIVISOR REGISTER
There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block.
The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate
(baud rate) as follows:
UBRDIVn = (int)( UART clock / ( buad rate x 16) ) –1
( UART clock : PCLK, FCLK/n or UEXTCLK )
Where, UBRDIVn should be from 1 to (216-1), but can be set zero only using the UEXTCLK which should be
smaller than PCLK.
For example, if the baud-rate is 115200 bps and UART clock is 40 MHz, UBRDIVn is:
UBRDIVn = (int)(40000000 / (115200 x 16) ) -1
= (int)(21.7) -1 [round to the nearest whole number]
= 22 -1 = 21
Register Address R/W Description Reset Value
UBRDIV0 0x50000028 R/W Baud rate divisior register 0 -
UBRDIV1 0x50004028 R/W Baud rate divisior register 1 -
UBRDIV2 0x50008028 R/W Baud rate divisior register 2 -
UBRDIV n Bit Description Initial State
UBRDIV [15:0] Baud rate division value UBRDIVn > 0
Using the UEXTCLK as input clock, UBRDIVn can be
set ‘0’.
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