Samsung S3C2440A - page 557

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA
27-39
Table 27-12 TFT LCD Controller Module Signal Timing Constants
(VDD = 1.2 V ± 0.05 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Units
Vertical Sync Pulse Width Tvspw VSPW + 1 – – Phclk (note1)
Vertical Back Porch Delay Tvbpd VBPD+1 – – Phclk
Vertical Front Porch Delay Tvf pd VFPD+1 – – Phclk
VCLK Pulse Width T vclk 1 – – Pvclk (note2)
VCLK Pulse Width High Tvclk h 0.5 – – Pvclk
VCLK Pulse Width Low Tvclkl 0.5 – – Pvclk
Hsync Setup To VCLK Falling Edge Tl2csetup 0.5 – – Pvclk
VDEN Setup To VCLK Falling Edge Tde2csetup 0.5 – – Pvclk
VDEN Hold From VCLK Falling Edge Tde2chold 0.5 – – Pvclk
VD Setup To VCLK Falling Edge Tvd2csetup 0.5 – – Pvclk
VD Hold From VCLK Falling Edge Tvd2chold 0.5 – – Pvclk
VSYNC Setup To HSYNC Falling Edge Tf2hsetup HSPW + 1 – – Pvclk
VSYNC Hold From HSYNC Falling Edge Tf 2hhold HBPD + HFPD +
HOZVAL + 3 – – Pvclk
NOTES:
1. HSYNC period
2. VCLK period
Table 27-13 IIS Controller Module Signal Timing Constants
(VDD = 1.2 V ± 0.1 V, TA = -40 to 85 °C, VEXT = 3.3V ± 0.3V)
Parameter Symbol Min Typ. Max Unit
IISLRCK delay time tLRCK 0 – 3 ns
IISDO delay time tSDO 1 – 2 ns
IISDI Input Setup time tSDIS 5 –
13 ns
IISDI Input Hold time tSDIH 0 – 1 ns
CODEC clock frequency fCODEC 1/16 – 1 fIIS_BLOCK