Ultra Fast USB 2.0
Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface.
The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. When “n” is not present before the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
6.1USB2640/USB2641 Pin Descriptions
Table 6.1 USB2640/USB2641 Pin Descriptions
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NAME | SYMBOL | QFN | TYPE | DESCRIPTION |
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| xD INTERFACE (APPLIES ONLY TO USB2640) | |||
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xD Write Protect | xD_nWP | 21 | O12PD | This pin is an active low write protect signal for the |
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| xD device. |
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| This pin has a weak |
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| permanently enabled. |
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xD Address | xD_ALE | 23 | O12PD | This pin is an active high Address Latch Enable |
Strobe |
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| signal for the xD device. |
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| This pin has a weak |
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| permanently enabled. |
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xD Command | xD_CLE | 24 | O12PD | This pin is an active high Command Latch Enable |
Strobe |
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| signal for the xD device. |
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| This pin has a weak |
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| permanently enabled. |
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xD Data | xD_D[7:0] | 30 | I/O12PD | These pins are the |
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| 32 |
| xD_D7 - xD_D0. |
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| 33 |
| The |
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| 13 |
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| 17 |
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| 18 |
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| 19 |
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| 20 |
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xD Read Enable | xD_nRE | 27 | O12PU | This pin is an active low read strobe signal for the |
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| xD device. |
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| When using the internal FET, this pin has an |
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| internal weak |
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| output of the internal Power FET and is controlled |
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| by the xD_PU bit of the xDC_CTL register. |
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| If an external FET is used (Internal FET is |
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| disabled), then the internal |
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| (external |
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SMSC USB2640/USB2641 | 17 | Revision 2.0 |
| DATASHEET |
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