Ultra Fast USB 2.0
Table 6.1 USB2640/USB2641 Pin Descriptions (continued)
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NAME | SYMBOL | QFN | TYPE | DESCRIPTION |
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SPI Clock | SPI_CLK / | 9 | I/O12 | SPI_CLK: This is the SPI clock out to the serial |
| GPIO4 / |
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| SCL |
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| for diagram and usage instructions. |
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| When the SPI interface is disabled, by setting the |
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| SPI_DISABLE bit in the UTIL_CONFIG1 register, |
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| this pin becomes GPIO4. |
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| During reset, this pin must be driven low. |
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| GPIO: This pin may be used either as input, edge |
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| sensitive interrupt input, or output. |
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| SCL: When configured, this is the I2C EEPROM |
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| clock pin. |
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SPI Data Out | SPI_DO / | 10 | I/O12 | SPI_DO: This is the data out for the SPI port. See |
| GPIO5 / SDA / |
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| Section 6.4, "ROM BOOT Sequence" for diagram |
| SPI_SPD_SEL |
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| and usage instructions. |
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| When the SPI interface is disabled, by setting the |
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| SPI_DISABLE bit in the UTIL_CONFIG1 register, |
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| this pin becomes GPIO5. |
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| GPIO: This pin may be used either as input, edge |
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| sensitive interrupt input, or output. |
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| SDA: This pin is the data pin when the device is |
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| connected to the optional I2C EEPROM. |
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| SPI_SPD_SEL: This pin is used to pick the speed |
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| of the SPI interface. During nRESET assertion, |
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| this pin will be |
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| resistor enabled. When nRESET is negated, the |
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| value on the pin will be internally latched, and the |
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| pin will revert to SPI_DO functionality, the internal |
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| 0 = 30 MHz |
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| 1 = 60 MHz |
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| The firmware can see the state of this bit in the |
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| SPI_CTL register. |
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| Note: |
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| If the latched value is '1', then the pin is |
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| when the chip is in the suspend state. |
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| If the latched value is '0', then the pin is driven low |
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| during a suspend state. |
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SPI Data In | SPI_DI | 11 | I/O12PD | This is the data in to the controller from the ROM. |
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| This pin must have a weak internal |
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| applied at all times to prevent floating. |
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SMSC USB2640/USB2641 | 21 | Revision 2.0 |
| DATASHEET |
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