MDS-NT1
Pin No. | Pin Name | I/O | Description | |
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41 | A11 | O | Address signal output to the external | |
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42 to 45 | D0 to D3 | I/O | ||
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46 | XCAS | O | Column address strobe signal output to the | |
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47 | XRAS | O | Row address strobe signal output to the | |
48 to 56 | A00 to A02, | O | Address signal output to the | |
A05 to A10 | ||||
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57 | VDC2 | — | Power supply terminal (+2.5V) (for core) | |
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58 | VSC2 | — | Ground terminal (for core) | |
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59, 60 | A03, A04 | O | Address signal output to the | |
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61 | DRVDD1 | — | Power supply terminal (+3.3V) (for | |
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62 | DRVSS1 | — | Ground terminal (for | |
63, 64 | TEST0, TEST1 | I | Not used | |
65 | TEST2 | O | Not used | |
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66 | AVD1 | — | Power supply terminal (+3.3V) (analog system) | |
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67 | ASYO | O | Playback EFM | |
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68 | ASYI | I | Playback EFM comparator slice voltage input | |
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69 | BIAS | I | Playback EFM comparator bias current input | |
70 | RFI | I | Playback EFM RF signal input from the RF amplifier | |
71 | AVS1 | — | Ground terminal (analog system) | |
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72 | PCO | O | Phase comparison output for master clock of the recording/playback EFM master PLL | |
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73 | FILI | I | Filter input for master clock of the recording/playback EFM master PLL | |
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74 | FILO | O | Filter output for master clock of the recording/playback EFM master PLL | |
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75 | CLTV | I | Internal VCO control voltage input of the recording/playback EFM master PLL | |
76 | PEAK | I | Light amount signal (RF/ABCD) peak hold input from the RF amplifier | |
77 | BOTM | I | Light amount signal (RF/ABCD) bottom hold input from the RF amplifier | |
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78 | ABCD | I | Light amount signal (ABCD) input from the RF amplifier | |
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79 | FE | I | Focus error signal input from the RF amplifier | |
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80 | AUX1 | I | Auxiliary signal (I3 signal/temperature signal) input from the RF amplifier | |
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81 | VC | I | Middle point voltage (+1.65V) input from the RF amplifier | |
82 | ADIO | O | Output terminal for the test | |
83 | ADRT | I | A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set) | |
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84 | ADRB | I | A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set) | |
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85 | SE | I | Sled error signal input from the RF amplifier | |
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86 | TE | I | Tracking error signal input from the RF amplifier | |
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87 | AVD2 | — | Power supply terminal (+3.3V) (analog system) | |
88 | AVS2 | — | Ground terminal (analog system) | |
89 | DCHG | I | Connected to the +3.3V power supply | |
90 | APC | I | Error signal input terminal for laser digital automatic power control Not used | |
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91 | ADFG | I | ADIP duplex FM signal (22.05 kHz ± 1 kHz) input from the RF amplifier | |
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92 | VDIO1 | — | Power supply terminal (+3.3V) (for I/O) | |
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93 | VSIO1 | — | Ground terminal (for I/O) | |
94 | F0CN | O | Filter f0 control signal output to the RF amplifier | |
95 | VDC3 | — | Power supply terminal (+2.5V) (for core) | |
96 | VSC3 | — | Ground terminal (for core) | |
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97 | XLRF | O | Serial data latch pulse signal output to the RF amplifier | |
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98 | CKRF | O | Serial data transfer clock signal output to the RF amplifier | |
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99 | DTRF | O | Writing serial data output to the RF amplifier | |
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