Sony 2008H05-1 SCD-XA5400ES, BLOCK DIAGRAM - MAIN Section, Signal Path Sa-Cd, Page 17 A Page 18 B

SCD-XA5400ES

6-3. BLOCK DIAGRAM - MAIN Section -

(Page 17) A

(Page 18) B

PDT, BDTR, PBCK,
PLRCK, SBCK	PDT			5	PDATA
						IOUTR+	17	BUFFER
	BDTR	SWITCHING		1	DSDL	IOUTR-	18	IC253
		IC206
			R-CH	2	DSDR
	PBCK			4	PBCK
	PLRCK
				6	PLRCK
	SBCK	INVERTER			D/A CONVERTER
		IC292	D-FLIP FLOP
						IC202
			IC155
						IOUTL+	25	BUFFER
						IOUTL-	26	IC203

27M

					7	SCK
		COUNTER
		IC156			3	AB CK
X151	CLOCK GENERATOR
22.5792MHz
		IC151			10	MS
CLOCK
BUFFER	2	REF	CLKP	15	11	MDI
IC152		SCL	SDA		12	MDO
					14	RST
		1	2

R-ch is omitted due to same as L-ch.

•SIGNAL PATH

: SA-CD

LOW-PASS FILTER	1	4	2
		3
IC255
RELAY DRIVE
Q252, 253
RY252	1	4	2
LOW-PASS FILTER
		3
IC205
RELAY DRIVE
Q202, 203
RY202		J251
BUFFER			R
IC204
		J201
			L
RELAY DRIVE	RV801
Q201, 204
RY201	PHONE LEVEL
RELAY
CONTROL
Q151, 293	-1
LINE AMP
IC291
	-2

J252

R

J202

L

ANALOG OUT

UNBALANCED

J801

PHONES

AC_DET C (Page 20)

78	77	87	88	30	28	85		6	19
ICPLLISC SCL	ICPLLI2C SDA	DAC CS2	DAC CS1	DAC DATA	DAC CLK	DAC INT	SYSTEM CONTROLLER	XAMUTE	ASDMUTE
							IC501 (3/4)

SCD-XA5400ES

19 19