BIOS Setup Utility |
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After you have completed the changes, press [Esc] and follow the instructions on your screen to save your settings or exit without saving. The following table describes each field in the Advanced Chipset Features Menu and how to configure each parameter.
3-4.1 CHIPSET FEATURES SETUP
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| FEATURES |
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DRAM Timing By
SPD
Disabled | If enable the DRAM will auto |
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Enabled | detect the DRAM timing | Default |
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DRAM Clock
SDRAM Cycle Length
100MHz | This item allows you to control the | Default |
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133MHz | DRAM speed. |
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3 | When synchronous DRAM is | Default |
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2installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.
Bank Interleave
Disabled Increase DRAM performance. Default
2 Bank
4 Bank
Memory Hole
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Disabled |
| Default |
Enabled | Some interface cards will map |
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PCI master Pipeline Req
P2C/C2P Concurrency
| Disabled | Disabled/Enabled PCI Master |
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| Enabled | Pipeline Req. | Default |
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| Disabled | This item allows you to |
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| Enabled | enable/disable the PCI to CPU, | Default |
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| CPU to PCI concurrency. |
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