Sun Microsystems S16A manual Current Count Registers, Control and Next Count Registers

S16A User’s Guide Registers

These registers hold the address of the next DMA transfer to be performed for each channel. When the current DMA transfer on a channel completes, if there is a “next” one set up, the contents of the Next DMA Address register for the channel are copied to the Current DMA Address register, the next count is copied to the Current DMA Count register, and the new transfer is started automatically.

Bit	Description
31–20	Show or store the 1 MB page addressed by the next DMA.
19–2	Show or store the address within the page for next DMA to use.
1–0	Set to 0. S16A DMA transfers must be 32-bit word-aligned.

Table 8. Next DMA Address Registers

Current Count Registers

The Current Count registers are 32-bit read-only registers at address 0x40008, 0x40018, 0x40028, and 0x40038, one for each channel. The second-lowest hexadecimal address digit specifies the DMA channel. The maximum byte count for a single DMA transfer is 1 MB. Each of these registers reflects the counter for the current DMA transfer in progress (if any) on it’s channel.

Bit	Description
31–20	Always 0.
19–2	When read, these bits display how many words remain in the DMA transfer currently in
	progress.
1–0	Always 0. S16A DMA transfers consist of whole 32-bit words.

Table 9. Current Count Registers

Control and Next Count Registers

The Control And Next Count registers are 32-bit registers at address 0x4000C, 0x4001C, 0x4002C, and 0x4003C. The second-lowest hexadecimal address digit specifies the DMA channel. These registers provide the transfer counts and control of the DMA hardware for each of the four DMA channels.

Bit	S16A_		Description
31	INT		A read-only status bit. A value of 1 indicates the S16A is asserting an SBus
			interrupt.
30			Unused. 0 when read.
29	DMA_START		A value of 1 enables DMA transfer.
28			Unused. 0 when read.
27	EN_EODMA		A value of 1 enables end-of-DMA interrupt.
26			Unused. 0 when read.
25	DMA_DIR_READ		DMA direction: a value of 1 reads host memory, 0 writes it. For channels 0
			& 1 must be 0; for channels 2 & 3 must be 1.
		Table 10. Control and Next Count Registers

EDT, Inc. October, 1996 29