Texas Instruments MSP-FET430 manual A.3 Debugging C-SPY, Frequently Asked Questions

Frequently Asked Questions

Optimization: NONE is supported within PROJECT->OPTIONS- >C/C++ COMPILER->CODE->OPTIMIZATIONS. Alternatively, variables can be declared volatile.

16)The IAR Tutorial assumes a Full or Baseline version of the Workbench. Within a Kickstart system, it is not possible to configure the C compiler to output assembler mnemonics.

17)Existing projects from an IAR 1.x system can be used within the new IAR 2.x/3.x system; refer to the IAR document Migration guide for EW430 x.x. This document can be located in: <Installation Root>\Embedded Workbench x.x\430\doc\migration.htm

18)Assembler projects must reference the code segment (RSEG CODE) in order to use the LINKER->PROCESSING->FILL UNUSED CODE MEMORY mechanism. No special steps are required to use LINKER ->PROCESSING->FILL UNUSED CODE MEMORY with C projects.

19)Numerous C and C++ libraries are provided with the Workbench:

cl430d:	C, 64-bit doubles
cl430dp:	C, 64-bit doubles, position independent
cl430f:	C, 32-bit doubles
cl430fp:	C, 32-bit doubles, position independent
dl430d:	C++, 64-bit doubles
dl430dp:	C++, 64-bit doubles, position independent
dl430f:	C++, 32-bit doubles
dl430fp:	C++, 32-bit doubles, position independent

A.3 Debugging (C-SPY)

1)C-SPY reports that it cannot communicate with the device. Possible solutions to this problem include:

Ensure that the correct PC port is selected; use PROJECT-

>OPTIONS->FET DEBUGGER->CONNECTIONS

Ensure that R6 on the MSP-FET430X110 and the FET Interface module has a value of 82 ohms. Early units were built using a 330 ohm resistor for R6. Refer to the schematics and pictorials of the MSP-FET430X110 and the FET Interface module presented in Appendix B to locate R6. The FET Interface module can be opened by inserting a thin blade between the case halves, and then carefully twisting the blade so as to pry the case halves apart.

Ensure that the correct parallel port (LPT1, 2, or 3) is being specified in the C-SPY configuration; use PROJECT->OPTIONS-> FET DEBUGGER->CONNECTIONS ->PARALLEL PORT->LPT1 (default) or LPT2 or LPT3. Check the PC BIOS for the parallel port address (0x378, 0x278, 0x3bc), and the parallel port configuration (ECP, Compatible, Bidirectional, or Normal). Refer to FAQ, Debugging #6) later in this document. For users of IBM Thinkpads, please try port specifications LPT2 and LPT3 despite the fact that the operating system reports the parallel port is located at LPT1.

Ensure that no other software application has reserved/taken control of the parallel port (say, printer drivers, ZIP drive drivers, etc.). Such

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