Texas Instruments MSP-FET430 manual Using an Existing IAR V1.x/V2.x Project

Development Flow

Note: How to add assembler source files to your project

The default file type presented in the Add Files window is “C/C++ Files”. In order to view assembler files (.s43), select “Assembler Files” in the “Files of type” drop-down menu.

8)Configure the project options (PROJECT->OPTIONS). For each of the listed subcategories (GENERAL OPTIONS, C/C++ COMPILER, ASSEMBLER, LINKER, DEBUGGER), accept the default Factory Settings with the following exceptions:

Specify the target device (GENERAL OPTIONS->TARGET->DEVICE)

Enable an assembler project or a C/assembler project (GENERAL OPTIONS ->TARGET->ASSEMBLER ONLY PROJECT)

Enable the generation of an executable output file (GENERAL OPTIONS -

>OUTPUT->OUTPUT FILE->EXECUTABLE)

To debug on the FET (i.e., the MSP430), select DEBUGGER ->SETUP-

>DRIVER-> FET DEBUGGER

Specify the active port used to interface to the FET (FET DEBUGGER - >SETUP->CONNECTION)

8)Build the project (PROJECT->REBUILD ALL).

9)Debug the application using C-SPY (PROJECT->DEBUG). This will start C- SPY, and C-SPY will get control of the target, erase the target memory, program the target memory with the application, and reset the target.

Refer to FAQ, Debugging #1) if C-SPY is unable to communicate with the device.

10)Use DEBUG->GO to start the application.

11)Use DEBUG->STOP DEBUGGING to stop the application, to exit C-SPY, and to return to the Workbench.

12)Use FILE->EXIT to exit the Workbench.

2.2.3Using an Existing IAR V1.x/V2.x Project

It is possible to use an existing project from an IAR V1.x/V2.x system with the new IAR V3.x system; refer to the IAR document Step by step migration for EW430 x.xx. This document can be located in: <Installation Root>\Embedded Workbench x.x\430\doc\migration.htm

2.2.4Stack Management within the .xcl Files

The .xcl files are input to the linker, and contain statements that control the allocation of device memory (RAM, Flash). Refer to the IAR XLINK documentation for a complete description of these files. The .xcl files provided with the FET (<Installation Root>\Embedded Workbench x.x\430\config\lnk430xxxx.xcl) define a relocatable segment (RSEG) called CSTACK. CSTACK is used to define the region of RAM that is used for the

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