2 Troubleshooting Procedures 2.4 System Board Troubleshooting

2-22 [CONFIDENTIAL] TECRA A9(S5/P5/S200) Maintenance Manual (960-633)

Table 2-5 Serial port (Boot mode) error status (3/9)
D port
Status
Test item Message
Renewal of a microcode （Only
support model）
Prohibition of cache
Permission of L1/L2 cache in
FlashROM area
Initialization of H/W (before
DRAM recognition)
Initialization of MCH
Initialization of ICH6M D30.Func0
Initialization of ICH6M.D31.Func0
Initialization of ICH6M.D31.Func1/2
Initialization of USB Controller
Initialization of ICH6M.D31.Func3
Initialization of ICH6M AC97 Audio
F100h
Initialization of TI Controller
Initialization of PIT channel 1 (Setting the refresh interval to “30μs”)
Check of DRAM type and size
(at cold boot)
When unsupported memory is connected, becoming
HLT after beep sound
F101h
SM-RAM stack area test HLT when DRAM size is 0
HLT When it can not be used as a stack
Cache configuration
Cache permission(L1/L2 cache)
CMOS access test
(at cold boot)
(HLT when an error is detected)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status (Setting of boot status and IRT busy flag, The rest bits
are 0)
F102h
Storing DRAM size in CMOS
Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
S3 returning error (1CH) (Resume error LED=7AH)
F103h Resume branch (at cold boot)
SM-RAM checksum check (Resume error
LED=73H)