R

Chapter 3: Quick Start Example Design

To run a VHDL or Verilog functional simulation of the example design using NCSIM:

1.Set the current directory to:

<quickstart>/simulation/functional/

2.Execute the simulation script:

% simulate_ncsim.sh ms-dos> simulate_ncsim.bat

To run a Verilog functional simulation of the example design using VCS:

1.Set the current directory to:

<quickstart>/simulation/functional/

2.Execute the simulation script:

% simulate vcs.sh

The simulation script compiles the functional simulation models, the loopback and the demonstration test bench, adds relevant signals to the wave window, and runs the simulation. To observe the operation of the core, inspect the simulation transcript and the waveform.

Timing Simulation

Timing simulation is available only with purchase of the core (Full license) or with access to the Full System Hardware Evaluation license. With a Simulation Only Evaluation license the core cannot be run through the implementation tools, which is required for timing based simulation.

Instructions for running a timing simulation of the SPI-4.2 core using either VHDL or Verilog are given below. A timing simulation model is generated when the core is run through the Xilinx tools using the implement script. Calendar information specified in a COE file is included in the timing simulation netlist.

To run a VHDL or Verilog l simulation of the example design using MTI:

1.Set the current directory to:

<quickstart>/simulation/timing/

2.Launch the ModelSim simulator.

3.Launch the simulation script: modelsim> do simulate_mti.do

To run a VHDL or Verilog simulation of the example design using NCSIM:

1.Set the current directory to:

<quickstart>/simulation/timing/

2.Execute the simulation script:

ms-dos> simulate_ncsim.bat % simulate_ncsim.sh

To run a Verilog simulation of the example design using VCS:

1.Set the current directory to:

<quickstart>/simulation/timing/

2.Execute the simulation script:

% simulate_vcs.sh

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Xilinx UG154 manual Timing Simulation
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UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.
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