Xilinx UG154 Timing Simulation

22 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide

UG154 March 24, 2008

Chapter 3: Quick Start Example Design

R

To run a VHDL or Verilog functional simulation of the example design using NCSIM:

1. Set the current directory to:

<quickstart>

/simulation/functional/

2. Execute the simulation script:

% simulate_ncsim.sh

ms-dos> simulate_ncsim.bat

To run a Verilog functional simulation of the example design using VCS:

1. Set the current directory to:

<quickstart>

/simulation/functional/

2. Execute the simulation script:

% simulate vcs.sh

The simulation script compiles the functional simulation models, the loopback and the

demonstration test bench, adds relevant signals to the wave window, and runs the

simulation. To observe the operation of the core, inspect the simulation transcript and the

waveform.

Timing Simulation

Timing simulation is available only with purchase of the core (Full license) or with access

to the Full System Hardware Evaluation license. With a Simulation Only Evaluation

license the core cannot be run through the implementation tools, which is required for

timing based simulation.

Instructions for running a timing simulation of the SPI-4.2 core using either VHDL or

Verilog are given below. A timing simulation model is generated when the core is run

through the Xilinx tools using the implement script. Calendar information specified in a

COE file is included in the timing simulation netlist.

To run a VHDL or Verilog l simulation of the example design using MTI:

1. Set the current directory to:

<quickstart>

/simulation/timing/

2. Launch the ModelSim simulator.

3. Launch the simulation script:

modelsim> do simulate_mti.do

To run a VHDL or Verilog simulation of the example design using NCSIM:

1. Set the current directory to:

<quickstart>/simulation/timing/

2. Execute the simulation script:

ms-dos> simulate_ncsim.bat

% simulate_ncsim.sh

To run a Verilog simulation of the example design using VCS:

1. Set the current directory to:

<quickstart>

/simulation/timing/

2. Execute the simulation script:

% simulate_vcs.sh

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages