Xilinx UG154 - page 46

46 www.xilinx.com SPI-4.2 v8.5 Getting Started Guide

UG154 March 24, 2008

Appendix A: VHDL Details

R

automatically calculated from the number of bytes sent. ERR has a higher priority than

EOP; if EOP and ERR are both ‘1’, the EOPs for the burst is an EOP abort = ‘01’.

The send_idles procedure is used to send idle control words.

The send_training procedure is used to send training patterns.

The sop_spacing procedure is used to send erro red data by se nding two SO Ps in less th an

eight cycles. This function limits the number of cycles between the two SOPs to less than

seven. This ensures that a SOP spacing error occurs.

Tabl e A -2 : send_user_data (PBr, SOP, EOP, Err, Addr, bytes) Inputs

Name Range Description

SOP 0 or 1 Defines if the packet should begin with a SOP.

EOP 0 or 1 Defines if the packet should be terminated with

an EOP.

ERR 0 or 1 Defines if the packet should be terminated with

an EOP abort.

ADDR 0 to 255 Channel on which the packet should be sent.

BYTES 1 to 255 Number of bytes to send on the selected channel.

Tabl e A -3 : send_idles (PBr, cycles) Inputs

Name Range Description

CYCLES 0 to 511 Number of idle control words to send on RDat.

Tabl e A -4 : send_training (PBr, patterns) Inputs

Name Range Description

PATTERNS 0 to 255 Number of training patterns to send.

Tabl e A -5 : sop_spacing (PBr, Bytes1, Err1, Addr1, EOP2, Err2, Addr2, Bytes2,

num_cycles) Inputs

Name Range Description

BYTES1 0 to 10 The number of bytes to send in the first burst.

This is limited to 10 bytes to ensure SOP spacing

is violated.

ERR1 0 or 1 Defines if the first packet should be terminated

with an EOP abort. If set to 0 the EOPs will be

calculated from BYTES1.

ADDR1 0 to 255 Channel on which the first packet should be sent.

EOP2 0 or 1 Defines if the second packet should be

terminated with an EOP.

ERR2 0 or 1 Defines if the second packet should be

terminated with an EOP abort. If set to 0 the

EOPs will be calculated from Bytes1.

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages