R

Appendix A: VHDL Details

automatically calculated from the number of bytes sent. ERR has a higher priority than EOP; if EOP and ERR are both ‘1’, the EOPs for the burst is an EOP abort = ‘01’.

Table A-2:send_user_data (PBr, SOP, EOP, Err, Addr, bytes) Inputs

Name

Range

Description

 

 

 

SOP

0 or 1

Defines if the packet should begin with a SOP.

 

 

 

EOP

0 or 1

Defines if the packet should be terminated with

 

 

an EOP.

 

 

 

ERR

0 or 1

Defines if the packet should be terminated with

 

 

an EOP abort.

 

 

 

ADDR

0 to 255

Channel on which the packet should be sent.

 

 

 

BYTES

1 to 255

Number of bytes to send on the selected channel.

 

 

 

The send_idles procedure is used to send idle control words.

Table A-3:send_idles (PBr, cycles) Inputs

Name

Range

Description

 

 

 

CYCLES

0 to 511

Number of idle control words to send on RDat.

 

 

 

The send_training procedure is used to send training patterns.

Table A-4:send_training (PBr, patterns) Inputs

Name

Range

Description

 

 

 

PATTERNS

0 to 255

Number of training patterns to send.

 

 

 

The sop_spacing procedure is used to send errored data by sending two SOPs in less than eight cycles. This function limits the number of cycles between the two SOPs to less than seven. This ensures that a SOP spacing error occurs.

Table A-5:sop_spacing (PBr, Bytes1, Err1, Addr1, EOP2, Err2, Addr2, Bytes2, num_cycles) Inputs

Name

Range

Description

 

 

 

BYTES1

0 to 10

The number of bytes to send in the first burst.

 

 

This is limited to 10 bytes to ensure SOP spacing

 

 

is violated.

 

 

 

ERR1

0 or 1

Defines if the first packet should be terminated

 

 

with an EOP abort. If set to 0 the EOPs will be

 

 

calculated from BYTES1.

 

 

 

ADDR1

0 to 255

Channel on which the first packet should be sent.

 

 

 

EOP2

0 or 1

Defines if the second packet should be

 

 

terminated with an EOP.

 

 

 

ERR2

0 or 1

Defines if the second packet should be

 

 

terminated with an EOP abort. If set to 0 the

 

 

EOPs will be calculated from Bytes1.

 

 

 

46

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

Page 46
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Xilinx UG154 manual Table A-3sendidles PBr, cycles Inputs Name Range Description

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

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