R

Appendix B

Verilog Details

Procedures Module

The procedures module is a package of functions instantiated in the Testcase module to simplify sending data and status to the Stimulus module. Use these functions to create any desired sequence of data or status. All functions are called from the Testcase module using the following format:

Format: tasks.<function name>(<inputs>)

Example: tasks.send_packet(0,40): A 40-byte long packet is sent on channel 0.

The procedures module handles all clocking for the Testcase module. For an example of how these procedures are used, see the default file (pl4_testcase.v) provided with the core.

The tables in this section describe the supported functions included in the procedures module.

The reset procedure is used to reset the interface to the Stimulus Module. This procedure should be called at the beginning of any testcase.

The send_packet procedure is used to transmit an entire packet of data. This procedure will always send a SOP control word before the burst of data and an EOP control word following the data burst. The EOPS (bits 14:13 of the control word following the burst) are automatically calculated from the number of bytes sent.

Table B-1:send_packet (Addr, bytes) Inputs

Name

Range

Description

 

 

 

ADDR

0 to 255

Channel on which the packet should be sent.

 

 

 

BYTES

1 to 255

Number of bytes to send on the selected channel.

 

 

 

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Xilinx UG154 manual Verilog Details, Procedures Module

UG154 specifications

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