Xilinx UG154 Verilog Details

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 49

UG154 March 24, 2008

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Appendix B

Verilog Details

Procedures Module

The procedures module is a package of functions instantiated in the Testcase module to

simplify sending data and status to the Stimulus module. Use these functions to create any

desired sequence of data or status. All functions are called from the Testcase module using

the following format:

Format: tasks.<function name>(<inputs>)

Example: tasks.send_packet(0,40): A 40-byte long packet is sent on

channel 0.

The procedures module handles all clocking for the Testcase module. For an example of

how these procedures are used, see the default file (pl4_testcase.v) provided with the

core.

The tables in this section describe the supported functions included in the procedures

module.

The reset procedure is used to reset the interface to the Stimulus Module. This procedure

should be called at the beginning of any testcase.

The send_packet procedure is used to transmit an entire packet of data. This procedure

will always send a SOP control word before the burst of data and an EOP control word

following the data burst. The EOPS (bits 14:13 of the control word following the burst) are

automatically calculated from the number of bytes sent.

Tabl e B -1 : send_packet (Addr, bytes) Inputs

Name Range Description

ADDR 0 to 255 Channel on which the packet should be sent.

BYTES 1 to 255 Number of bytes to send on the selected channel.

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages