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Xilinx UG154 manual 11Useful Testcase Signals Name Description

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Chapter 4: Detailed Example Design

Table 4-11contains a list of common useful test case signals and descriptions.

Table 4-11:Useful Testcase Signals

Name

Description

 

 

FullVec

An array of bits indicating the last status received on RStat for

 

each channel. For each channel, the corresponding bit is set (1)

 

if the status received was ‘10’ - satisfied, and cleared (0) if the

 

status was ‘01’ - hungry or ‘00’ - starving.

 

 

NumLinks

The number of channels for which the core was configured.

 

 

Reset_n

Reset signal to the Sink and Source core (active low).

 

 

SnkEn

Enable signal to the Sink core.

 

 

SnkFifoReset_n

FIFO Reset signal to the Sink core (active low).

 

 

SnkInFrame

Asserted when the Sink core is in frame (as interpreted by the

 

status monitor).

 

 

SnkOof

Out-of-Frame signal from the Sink core.

 

 

SrcEn

Enable signal to the Source core.

 

 

SrcFifoReset_n

FIFO Reset signal to the Source core (active low).

 

 

SrcInFrame

Asserted when the Source core is in frame (as interpreted by

 

the data monitor).

 

 

SrcOof

Out-of-Frame signal from the Source core.

 

 

There are five request signals that can be asserted in the testcase module. The first four signals interface to the stimulus module (see Figure 4-2, page 34). The fifth is encapsulated with the generated data sent to the stimulus module. Table 4-12details request signals.

Table 4-12:Testcase Module Request Signals

Name

Function

 

 

TCIdleRequest

Drives the IdleRequest input to the Source core, which results

 

in idles begin transmitted on TDat.

 

 

TCTrainingRequest

Drives the TrainingRequest input to the Source core, which

 

causes training to be sent on TDat.

 

 

TCSnkDip2ErrRequest

Drives the SnkDip2ErrRequest input to the Sink core, which

 

results in DIP2 errors on RStat.

 

 

TCDIP2Request

When asserted (active high), causes DIP2 errors to be

 

transmitted on TStat.

 

 

TCDIP4Request

When asserted (active high), causes DIP4 errors to be

 

transmitted on RDat.

 

 

In addition to the request signals described above, the test case module has control over the Sink and Source cores with the SnkEn, SrcEn, SnkFifoReset_n, and SrcFifoReset_n signals. Descriptions of these signals can be found in the SPI-4.2 Core User Guide.

The Source core status is also generated in the test case module using functions contained in the procedures module. Using the function send_status, you can specify a channel

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Xilinx UG154 manual 11Useful Testcase Signals Name Description, 12Testcase Module Request Signals Name Function
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UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

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