Xilinx UG154 manual Procedures Module, Data Monitor, Status Monitor

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Chapter 4: Detailed Example Design

Procedures Module

The procedures module is a package of functions instantiated in the testcase module to simplify sending data and status to the stimulus module. Using these functions, you can create any desired sequence of data or status. The method by which functions are called varies among languages, and is described in the appendices.

The following functions are supported in the procedures module:

•send_packet Used to transmit an entire packet of data. This procedure will always send an SOP control word before the burst of data and an EOP control word following the data burst.

•send_user_data Used to transmit a burst of data. The presence of an SOP control word (before the burst of data) and an EOP control word (following the data burst) can be specified. The EOP can optionally specify an abort (ERR).

•send_idles Used to send idle cycles.

•send_training Used to send training patterns.

•sop_spacing Used to send erred data by sending two SOP words in less than eight cycles. This function limits the number of cycles between the two SOPs to less than seven. This ensures that an SOP spacing error occurs.

•reset Used to reset the interface to the stimulus module. Should be called at the beginning of any testcase.

•send_status Used to change the status (on TStat) for a particular channel.

•get_status Used to check the status of a specific channel.

Data Monitor

The data monitor is responsible for verifying that data sent from the demonstration test bench is the same as the data received from the core. This is accomplished by monitoring the RDat and RCtl signals that are input into the Sink core, and comparing them to the TCtl and TDat signals output from the Source core. This is a simple comparison as long as the data being sent does not violate the OIF-SPI4-02.1specification. If the specification is violated, the SPI-4.2 core modifies the data to enforce compliance, and the data monitor accounts for the modification before comparing TDat to RDat. In addition to the data, the monitor also verifies DIP4, SOP spacing, IDLE request, Training request, DATA_MAX_T, and ALPHA_DATA compliance. Changes in the testcase can create situations that cause the data monitor to output warning messages. For more information on output warning messages, see Appendix C, “Data and Status Monitor Warnings.”

Status Monitor

The status monitor inspects the RStat bus. In addition to verifying correct values for channel status, it compiles the current status for each channel into the vector FullVec. FullVec is used by the testcase module when the CHECK_RSTAT constant is set to stall data on RDat when the targeted channel is full. See Table 4-11for more information about the FullVec vector.

The status monitor also calculates the DIP2 value for RStat and compares it with what is actually received. If there is an error, it looks at the signal SnkDIP2ErrRequest to see if it was asserted and the error is expected.

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		UG154 March 24, 2008