Xilinx UG154 - page 47

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 47

UG154 March 24, 2008

Procedures Module

R

The send_status procedure is used to change the status for a particular channel.

The get_status procedure is called to check status of a specific channel. It will cause the

status value of that channel to be returned to the testcase.

ADDR2 0 to 255 Channel on which the second packet should be

sent.

BYTES2 1 to 255 The number of bytes to send in the second burst.

NUM_CYCLES 0 to [5 - roundup

(BYTES1/2)]

The number of idle cycles between the first and

second burst.

Tabl e A -6 : send_status (PBt, channel, value) Inputs

Name Range Description

CHANNEL 0 to 255 Defines the channel for which status is updated.

VALUE 00,01,10,11 Defines the new status value to assign to the

selected channel.

Tabl e A -7 : get_status (PBt, channel) Inputs

Name Range Description

CHANNEL 0 to 255 Defines the channel for which status is read.

Tabl e A -5 : sop_spacing (PBr, Bytes1, Err1, Addr1, EOP2, Err2, Addr2, Bytes2,

num_cycles) Inputs (Continued)

Name Range Description

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages