Xilinx UG154 About This Guide

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 11

UG154 March 24, 2008

R

Preface

About This Guide

This guide provides information about generating the Xilinx LogiCORE™ IP SPI-4.2 core,

customizing and simulating the core using the provided example design, and running the

design files through implementation using the Xilinx tools.

Contents

This guide contains the following chapters:

•Preface, “About this Guide” introduces the organization and purpose of the Getting

Started Guide, and the conventions used in this document.

•Chapter 1, “Introduction” describes the core and related information, including

recommended design experience, additional resources, technical support, and

submitting feedback to Xilinx.

•Chapter 2, “Licensing the Core” provides information about installing and licensing

the core.

•Chapter 3, “Quick Start Example Design” provides instructions to quickly generate

the core and run the example design through implementation and simulation using

the default settings.

•Chapter 4, “Detailed Example Design” describes the files and directories created by

the CORE Generator. It also contains detailed information about the demonstration

test bench and directions for customizing it for use in a user application.

•Appendix A, “VHDL Details” provides details about the VHDL demonstration test

bench and how to customize it.

•Appendix B, “Verilog Details” provides details about the Verilog demonstration test

bench and how to customize it.

•Appendix C, “Data and Status Monitor Warnings” describes the common

demonstration test bench warnings.

Conventions

This document uses the following conventions. An example illustrates each convention.

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages