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Xilinx UG154 Implementing the Example Design, Running the Simulation, Setting up for Simulation

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Implementing the Example Design

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Implementing the Example Design

After generating a core with a Full System Hardware Evaluation or Full license, the netlists and the example design can be processed by the Xilinx implementation tools. The generated output files include scripts to assist you in running the Xilinx tools.

To implement the SPI-4.2 example design, open a command prompt or terminal window and type the following commands:

For Windows

ms-dos>cd <proj>\<quickstart>\implement ms-dos>implement.bat

For Linux

%cd <proj>/<quickstart>/implement

%./implement.sh

These commands execute a script that synthesizes, builds, maps, and place-and-routes the example design. The script then generates a post-par simulation model for use in timing simulation. The resulting files are placed in the results directory.

Running the Simulation

Using the provided example design, you can quickly simulate and observe the behavior of the SPI-4.2 core. There are two different simulation types, functional and timing. The simulation models provided are either in VHDL or Verilog, depending on the CORE Generator Design Entry project option selected by the user.

Setting up for Simulation

The Xilinx UniSim and SimPrim libraries must be mapped into the simulator. If the UniSim or SimPrim libraries are not set for the test environment, go to www.xilinx.com/support, where the following solution records are located:

•Compiling Xilinx Simulation Libraries (MTI) - Answer Record 2561

•Compiling Xilinx Simulation Libraries (NC-SIM) - Answer Record 2554

Functional Simulation

Instructions for running a functional simulation of the SPI-4.2 core using either VHDL or Verilog are given below. Functional simulation models are provided when the core is generated. Note that implementing the core before simulating the functional models is not required. If a configuration file (referenced in the CORE Generator GUI as the COE file) was used to program the calendar, special steps are required to include the calendar sequence in the simulation. See the SPI-4.2 Core User Guide for details on including the calendar initialization values in simulation.

To run a VHDL or Verilog functional simulation of the example design using MTI:

1.Set the current directory to:

<quickstart>/simulation/functional/

2.Launch the ModelSim® simulator.

3.Launch the simulation script: modelsim> do simulate_mti.do

SPI-4.2 v8.5 Getting Started Guide

www.xilinx.com

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UG154 March 24, 2008

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Xilinx UG154 Implementing the Example Design, Running the Simulation, Setting up for Simulation, Functional Simulation
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UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.