Xilinx UG154 Detailed Example Design

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 25

UG154 March 24, 2008

R

Chapter 4

Detailed Example Design

This chapter provides detailed information about the example design, including a

description of files and the directory structure generated by the Xilinx CORE Generator,

the purpose and contents of the provided scripts, the contents of the example HDL

wrappers, and the operation of the demonstration test bench.

top directory link - white text invisible

<project directory>topdirectory

Top-level project directory; name is user-defined

<project directory>/<component name>

Core release notes fi le

<component name>/doc

Product documentation

<component name>/example design

Verilog and VHDL design files

<component name>/implement

Implementation script files

implement/results

Results directory created after implementation scripts are run;

contains implement script results.

<component name>/simulation

Simulation scripts

simulation/functional

Functional simulation files

simulation/timing

Timing simulation files

Contents

Main SPI-4.2 v8.5 Getting Started Guide www.xilinx.com UG154 March 24, 2008 Revision History Page Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Appendix A: VHDL Details Procedures Module Appendix B: Verilog Details Procedures Module Random Testcase Sample Code Schedule of Figures Page Schedule of Tables Chapter 4: Detailed Example Design Appendix A: VHDL Details Appendix B: Verilog Details Page Preface About This Guide Contents Conventions Typographical Online Document design_name option_name design_name Introduction System Requirements Windows Linux Software Additional Core Resources Technical Support Feedback Core Document Licensing the Core Before you Begin License Options Simulation-Only Evaluation Full System Hardware Evaluation Obtaining Your License Obtaining a Simulation-Only or Full System Hardware Evaluation License Obtaining a Full License Installing Your License File Page Chapter 3 Quick Start Example Design Overview Generating the Core Page Implementing the Example Design Running the Simulation Setting up for Simulation Functional Simulation Timing Simulation Page Page Chapter 4 Detailed Example Design Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement implement/results <component name>/simulation simulation/functional simulation/timing Implementation and Simulation Scripts Simulation Script Details Example Design Configuration Loopback Module Basic Loopback Operation Demonstration Test Bench Demonstration Test Bench SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35 UG154 March 24, 2008 Status Monitor Test cas e Figure 4-3: Test Bench Modules Clock Generator Startup Module DCM Startup Calendar Loader DPA Initialization Stimulus Module Procedures Module Data Monitor Status Monitor Customizing the Demonstration Test Bench Test Case Package Page Testcase Module Page Calendar Sequence Files (Sink and Source) Page Appendix A VHDL Details Procedures Module Page Page Page Appendix B Verilog Details Procedures Module Page Random Testcase Sample Code Appendix B: Verilog Details Random Testcase Sample Code Appendix B: Verilog Details Appendix C Data and Status Monitor Warnings Page Appendix D Timing Simulation Warning and Error Messages