Xilinx UG154 manual Startup Module, 4Startup State Diagram

Models: UG154

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Chapter 4: Detailed Example Design

Startup Module

The Startup Module contains three functions: DCM setup, calendar loading, and Dynamic Phase Alignment (DPA) Initialization. These functions are described in detail in the following sections.

DCM Startup

The DCM Startup is a state machine that ensures that the DCMs are reset in the appropriate order. If they are not reset appropriately, the DCMs will not lock. The Startup Module first asserts DCMReset_TDClk. Once Locked_TDClk is asserted, it resets DCMReset_RDClk. Then it waits for Locked_RDClk before asserting DCMReset_TSClk. After Locked_TSClk is asserted, the state machine waits until the SnkClksRdy and SrcClksRdy signals are asserted. The Reset_n signal is deasserted only after this occurs. All operations are performed in the SysClk domain.

Count < 8

Count < 512 &

Locked_TDClk = 0

 

 

TDCLK_RST

Count = 8

TDCLK_LCK

 

DCMReset_TDClk = 1

DCMReset_TDClk = 0

 

 

 

DCMReset_RDClk = 0

 

DCMReset_RDClk = 0

1

Reset_n = 0

Count = 512

Reset_n = 0

 

 

Locked_TDClk = 1

Reset_n

IDLE

DCMReset_TDClk = 0

DCMReset_RDClk = 0 Reset_n = 0

Count < 8

RDCLK_RST

DCMReset_TDClk = 0

DCMReset_RDClk = 1

Reset_n = 0

Count = 512

Count = 8

 

RELEASE_RST

 

 

 

DCMReset_TDClk = 0

 

RDCLK_LCK

1

DCMReset_RDClk = 0

Count < 512 &

DCMReset_TDClk = 0

SnkClksRdy = 1

Locked_RDClk = 0

DCMReset_RDClk = 0

 

SrcClksRdy = 1

 

 

Reset_n = 0

 

Reset_n = 0

 

 

 

 

 

SnkClksRdy = 1 &

 

 

 

SrcClksRdy = 0

Locked_RDClk = 1

 

CLKS_RDY

SnkClksRdy = 1

SrcClksRdy = 1

SnkClksRdy = 0 or

SrcClksRdy = 0

Figure 4-4:Startup State Diagram

Figure 4-4illustrates the nine states for this machine.

IDLE Initial state after reset; DCMReset_TDClk is asserted.

TDCLK_RST Holds DCMReset_TDClk for 8 cycles then releases it.

TDCLK_LCK Waits for the Locked_TDClk signal.

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SPI-4.2 v8.5 Getting Started Guide

 

 

UG154 March 24, 2008

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Xilinx UG154 manual Startup Module, 4Startup State Diagram

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

Another key aspect highlighted in UG154 is the technological advancements in the latest Xilinx architectures, such as UltraScale and UltraScale+. These architectures incorporate advanced process technologies, providing improved performance and power efficiency. High-speed serial transceivers, embedded processing capabilities, and extensive memory options are also discussed, showcasing how these features enhance system integration and reduce design time.

The guide also delves into Xilinx's software ecosystem, featuring the Vivado Design Suite, which streamlines the design process through integrated design tools and a unified development environment. The Vivado suite supports various high-level synthesis, simulation, and analysis tools, facilitating a smoother transition from concept to implementation.

In addition to hardware and software integration, UG154 covers the importance of IP cores, which are pre-designed functional blocks that can be easily integrated into FPGA designs. Xilinx provides a vast library of IP cores, ranging from basic logic functions to sophisticated signal processing algorithms, enabling engineers to accelerate development without sacrificing performance.

Another focus of UG154 is the emphasis on design best practices and optimization techniques that can be employed to maximize the capabilities of Xilinx devices. Topics such as timing closure, resource optimization, and power management are among the critical areas addressed, which help designers achieve the desired performance within the constraints of their applications.

Overall, Xilinx UG154 serves as a vital resource that equips engineers with the knowledge and tools necessary to leverage the full potential of Xilinx FPGAs. By understanding the features, technologies, and architectural characteristics detailed within this guide, designers can create innovative solutions across a range of applications, including telecommunications, automotive, aerospace, and industrial automation.