Xilinx UG154 manual Timing Simulation Warning and Error Messages

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Appendix D

Timing Simulation Warning and Error Messages

There are several common simulation warnings and error messages when timing simulation is run on the example design. These warnings and messages are described in this appendix.

"# TDat Error: Data Mismatch # 4. Expected 000f, Received 000x. 339280 ps"

The data mismatch results from the data going to unknown "x" state. To prevent "x" from propagating in your simulation, use the "+no_notifier" option to vsim command when using ModelSim Simulator (MTI). If you are using other simulators, consult the manufacturer documentation for possible ways to turn off "x" propagation.

SETUP, HOLD, RECOVERY violation on /X_FF

These violations might come from either the Sink core or Source Core, and they originated from register elements that are transiting between two clock domains. These timing violations can be safely ignored.

When running simulation on a SPI-4.2 Sink Core with Global Clocking and DPA Clock Adjustment option, the signal Locked_RDClk (from RDClk DCM) might get deasserted after PhaseAlignRequest is asserted. When the PhaseAlignRequest has been asserted, the IDELAY goes through the reset process and the clock stops toggling momentarily. This might cause the lock signal from the DCM to get deasserted in simulation (this does not occur in hardware testing). Locked_RDClk should be ignored after the PhaseAlignRequest has been asserted in simulation.

"Memory Collision Error on X_RAMB16"

The "Memory Collision" error occurs occasionally because the calendar block is trying to read out values at the same time that you are writing them in; however, this is not a problem because you are only supposed to write the calendar when the core is disabled.

SPI-4.2 v8.5 Getting Started Guide

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UG154 March 24, 2008

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Xilinx UG154 manual Timing Simulation Warning and Error Messages, SETUP, HOLD, Recovery violation on /XFF

UG154 specifications

Xilinx UG154 is a comprehensive user guide that provides in-depth information about the architecture, features, and technologies of Xilinx's FPGA (Field Programmable Gate Array) devices. This guide is particularly vital for developers, engineers, and designers who work with Xilinx products, as it serves as a key resource throughout the development lifecycle.

One of the main features of Xilinx UG154 is its coverage of the device architecture, which details the programmable logic cells, configurable interconnects, and I/O capabilities. Xilinx FPGAs are known for their flexibility and scalability, allowing designers to implement complex digital circuits and systems that can be modified post-manufacturing, enabling rapid prototyping and iterative design processes.

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