York 00497VIP Liquid Crystal Display, Refer To, ment Displays or supporting components cannot be

FORM 50.40-OM2

LIQUID CRYSTAL DISPLAY

(REFER TO FIG. 37 - 42)

A 10.4 inch color Liquid Crystal Display, along with supporting components Display Interface Board and Backlight Inverter Board are mounted on a plate that is attached to the OptiView Control Center door. A clear plexiglass faceplate prevents display surface damage. System operating parameters are displayed on various color graphic screens. The various display screens are selected for display using the Keypad keys.

The Display provided in the OptiView RCC or from YORK as a service replacement part, could be manufac- tured by any of several approved manufacturers. Each Display requires a specific Display Interface Board, Backlight Inverter Board, Inverter Board interface cable and Program command set. Therefore, Service replace-

ment Displays or supporting components cannot be

arbitrarily selected!!! As explained below, replacement Displays are provided from YORK as kits to assure compatibility of all components. Non-compatibility of components will result in incorrect operation!!! Refer to “Display Interface Board” and “Backlight Inverter Board” descriptions that follow. The following displays could be provided from YORK in new OptiView RCCs or as replacement parts:

•LG SEMICON LP104V2

•SHARP LQ10D367

The YORK part numbers of the Display Interface Board, Backlight Inverter Board and Inverter ribbon cable provided, are listed on a label attached to the Display mounting plate. These are the part numbers of the supporting components that are compatible with the installed display. These supporting components can be individually replaced. However, if the Liquid Crystal Display fails, Display replacement kit 331-02053-000 must be ordered as detailed below. This kit contains a replacement Display and all compatible supporting components.

The Display has 307,200 pixels arranged in a 640 columns X 480 rows matrix configuration. Each pixel consists of 3 windows; red, green and blue, through which a variable amount of light from the Display Backlight is permitted to pass through the front of the display. Imbedded in each window of the pixel is a transistor, the conduction of which determines the amount of light that will pass through the window. The conduction of each transistor is controlled by a signal from the Display Controller on the Microboard. The overall pixel color is a result of the gradient of red, green and blue light allowed to pass.

Under Program control, the Display Controller on the Microboard sends a drive signal for each pixel to create the image on the display. Each pixel’s drive signal is an 18 bit binary word; 6 bits for each of the 3 colors, red green and blue. The greater the binary value, the greater the amount of light permitted to pass. The columns of pixels are driven from left to right and the rows are driven top to bottom. To coordinate the drive signals and assure the columns are driven from left to right and the rows are driven from top to bottom, each drive signal contains a horizontal and vertical sync signal. The Display Interface Board receives these display drive signals from the Microboard J5 and applies them to the Display at connector CN1. Refer to Fig. 43.

Although there are variations in control signal timing between different display manufacturers, Fig. 38 depicts typical control signals. Since these control signals occur at rates greater than can be read with a Voltmeter, the following description is for information only. There are 480 horizontal rows of pixels. Each row contains 640

3-window pixels. Beginning with the top row, the drive signals are applied within each row, sequentially left to right, beginning with the left most pixel and ending with the right most pixel. The rows are driven from top to bottom. The Vertical Sync (VSYNC) pulse starts the scan in the upper left corner. The first Horizontal Sync (HSYNC) pulse initiates the sequential application of RGB drive signals to the 640 pixels in row 1. Upon receipt of the ENABLE signal, an RGB drive signal is applied to the first pixel. As long as the ENABLE signal is present, RGB drive signals are then applied to the remaining 639 pixels at the CLK rate of 25.18MHz,

or one every 39.72 nanoseconds. Typically it takes 31 5 microseconds to address all 640 pixels. Similarly, the

next HSYNC pulse applies drive signals to row 2. This continues until all 480 rows have been addressed. Total elapsed time to address all 480 rows is approximately 16 milliseconds. The next VSYNC pulse causes the above cycle to repeat. Displays can be operated in FIXED mode or DISPLAY ENABLE mode. In FIXED mode, the first pixel drive signal is applied a fixed number

(48)of clock (CLK) cycles from the end of the HSYNC pulse and the drive signals are terminated a fixed number

(16)of CLK cycles prior to the next HSYNC pulse. In DISPLAY ENABLE mode, the pixel drive signals are applied to the pixels only while ENABLE signal is present. This signal is typically present 4-48 CLKS after the end of the HSYNC pulse and 2-16 CLKS prior

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