Intel IQ80333 manual Jtag Debug, Jtag Port Pin-out

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Intel® IQ80333 I/O Processor

Hardware Reference Section

3.7.2JTAG Debug

The 80333 has a 20-pin JTAG connector (J7D2) that is in compliant with ARM Multi-ICE guidelines.

3.7.2.1JTAG Port

Figure 9.	JTAG Port Pin-out


	VTref		1	2	Vsupply
	nTRST		3	4	GND
	TDI		5	6	GND
	TDI		5	6	GND
	TMS		7	8	GND
	TCK		9	10	GND
	RTCK		11	12	GND
	TDO		13	14	GND
	nSRST		15	16	GND

	DBGRQ		17	18	GND
	DBGACK		19	20	GND

A9457-01

36	Customer Reference Board Manual

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Contents Intel IQ80333 I/O Processor Customer Reference Board ManualCustomer Reference Board Manual Contents Dram 2.2 Figures Tables Revision History Date Revision DescriptionDocument Purpose and Scope Other Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80333 I/O Processor Intel 80333 I/O Processor Block Diagram 231Summary of Features Feature DefinitionKit Content Hardware InstallationFirst-Time Installation and Test Power Requirements Factory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedHat RedBoot Target MonitorsHost Communications Examples Serial-UART CommunicationJtag Debug Communication Network Communication Network Communication ExampleCommunicating with RedBoot GNUPro GDB/InsightIntel IQ80333 I/O Processor Connecting with GDB GDB set remotebaudThis Page Left Intentionally Blank Functional Diagram Target MarketPCI Express RAID card Form-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup Memory SubsystemFlash Memory Requirements Flash Memory RequirementsInterrupt Routing External Interrupt Routing to Intel 80333 I/O ProcessorPeripheral Bus Features 80333 populates the peripheral bus as depicted by FigureFlash ROM Features Flash ROMFlash Connection on Peripheral Bus Rotary Switch Uart Non-Volatile RAM Audio BuzzerBattery Status Battery Status Buffer RequirementsName Description Debug Interface Console Serial PortJtag Debug Jtag PortJtag Port Pin-out Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryDefault Switch Settings of S7A1- Visual Switch SummaryConnector Summary Jumper SummaryGeneral Purpose Input/Output Header Detail Descriptions of Switches/Jumpers Switch S1C2 Intel 80333 I/O Processor ResetSwitch S6A1 BPCI-X Reset Switch S8A1 RotarySwitch S7A1-2 Reset IOP Settings and Operation Mode Switch S7A1-3 Retry Settings and Operation ModeS7A1-4 PCI-X Bus B Speed Enable Settings and Operation Mode S7A1-8 Operation Mode S7A1-9 Operation ModeS7A1-10 Operation Mode Jumper J7D1 Flash bit-width Jumper J1C1 Jtag ChainJumper J1D2 Uart Control Jumper J9D3 Buzzer Volume Control Jumper J7B4 SMBus HeaderDram Components on the Peripheral BusFlash Connection to Peripheral Bus Peripheral Bus Memory Map Address Range in Hex Size Data Bus Width DescriptionBoard Support Package BSP Examples Intel 80333 I/O Processor Memory MapRedBoot* Intel 80333 I/O Processor Memory Map RedBoot Intel 80333 I/O Processor FilesVirtual Address Physical Address Size Description Mov R8, r4 IQ80321 and IQ80333 Comparisons This Page Left Intentionally Blank Introduction PurposeRelated Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Using Breakpoints Displaying Source CodeSetting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping