Intel IQ80333 manual Flash Memory Requirements

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Intel® IQ80333 I/O Processor

Hardware Reference Section

3.4.2Flash Memory Requirements

Total Flash memory size is 8 MB.

Table 8. Flash Memory Requirements

Description

IQ80333 Total Flash size is 8 MB

80333 Flash technology is based on Intel StrataFlash® family

80333 Flash uses a 16-bit interface

80333 Flash utilizes the 80333 Peripheral Bus

80333 May be programmed using the PCI-X interface – Flash Recovery Utility (FRU) Utility

80333 May be programmed using a RAM based software target monitor – RedHat RedBoot and ARM Firmware Suite

80333 May be programmed using a JTAG emulation/debug device

Customer Reference Board Manual

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Contents Customer Reference Board Manual Intel IQ80333 I/O ProcessorCustomer Reference Board Manual Contents Dram 2.2 Figures Tables Date Revision Description Revision HistoryOther Related Documents Document Purpose and ScopeComponent References Electronic InformationElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80333 I/O Processor 231 Intel 80333 I/O Processor Block DiagramFeature Definition Summary of FeaturesFirst-Time Installation and Test Kit ContentHardware Installation Power Requirements Contents of the Flash Factory SettingsDevelopment Strategy Supported Tool BucketsTarget Monitors RedHat RedBootJtag Debug Communication Host Communications ExamplesSerial-UART Communication Network Communication Example Network CommunicationGNUPro GDB/Insight Communicating with RedBootIntel IQ80333 I/O Processor GDB set remotebaud Connecting with GDBThis Page Left Intentionally Blank PCI Express RAID card Functional DiagramTarget Market Board Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerMemory Subsystem Battery BackupFlash Memory Requirements Flash Memory RequirementsExternal Interrupt Routing to Intel 80333 I/O Processor Interrupt Routing80333 populates the peripheral bus as depicted by Figure Peripheral Bus FeaturesFlash Connection on Peripheral Bus Flash ROM FeaturesFlash ROM Uart Rotary SwitchNon-Volatile RAM Audio BuzzerName Description Battery StatusBattery Status Buffer Requirements Console Serial Port Debug InterfaceJtag Port Pin-out Jtag DebugJtag Port Reset Requirements/Schemes Board Reset SchemeSwitch Summary Switches and JumpersDefault Switch Settings of S7A1- Visual Switch SummaryGeneral Purpose Input/Output Header Connector SummaryJumper Summary Switch S1C2 Intel 80333 I/O Processor Reset Detail Descriptions of Switches/JumpersSwitch S6A1 BPCI-X Reset Switch S8A1 RotaryS7A1-4 PCI-X Bus B Speed Enable Settings and Operation Mode Switch S7A1-2 Reset IOP Settings and Operation ModeSwitch S7A1-3 Retry Settings and Operation Mode S7A1-10 Operation Mode S7A1-8 Operation ModeS7A1-9 Operation Mode Jumper J1D2 Uart Control Jumper J7D1 Flash bit-widthJumper J1C1 Jtag Chain Jumper J7B4 SMBus Header Jumper J9D3 Buzzer Volume ControlComponents on the Peripheral Bus DramFlash Connection to Peripheral Bus Address Range in Hex Size Data Bus Width Description Peripheral Bus Memory MapIntel 80333 I/O Processor Memory Map Board Support Package BSP ExamplesVirtual Address Physical Address Size Description RedBoot* Intel 80333 I/O Processor Memory MapRedBoot Intel 80333 I/O Processor Files Mov R8, r4 IQ80321 and IQ80333 Comparisons This Page Left Intentionally Blank Purpose IntroductionRelated Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashManually Loading and Executing an Application Program Launching and Configuring DebuggerRunning the CodeLab Debugger Displaying Source Code Using BreakpointsStepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping