Intel IQ80219 manual ARM Firmware Suite

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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Getting Started

2.5.2ARM Firmware Suite

The ARM Firmware Suite is a package of low-level routines and libraries that have been designed to help developers rapidly bring up applications and operating systems on Intel XScale® microarchitecture-based development platforms, such as the IQ80219.

AFS consists of two parts:

1.µHAL, the ARM standard board API, which is low-level firmware, designed to provide a common set of functions across IQ80219. These include

System initialization software.

Simple polled serial drivers.

LED support.

Timer support.

Interrupt Controller support.

µHAL manages all the variables associated with the IQ80219. This is provided in source form for users to embed and distribute in their own products running on an 80219. Included also as sources and with object distribution rights are:

A simple boot monitor.

Event chaining libraries, low level ADS C++ support libraries, benchmarking and demonstration applications.

Angel* debug target and host communication software that allows inter-working with ARM Developer Suite.

2.On top of µHAL, AFS provides some useful applications, demos and example operating systems such as µCOS-II. The applications are currently.

Flash Library supporting a range of commonly used Flash parts.

Flash management utilities including support for multiple Flash images using the ARM Flash format standard.

PCI Library that fully initializes the PCI subsystem and provides device driver primitives.

DHCP Client over Ethernet of the fast download of binary images into Flash or RAM.

Full on line documentation.

Example OS ports.

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Contents Board Manual November 13Board Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Rstmode and Retry Operation Setting Summary Tables105 Revision History Date Revision DescriptionThis Page Left Intentionally Blank Document Purpose and Scope Related DocumentsElectronic Information Electronic InformationComponent References Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80219 General Purpose PCI Processor Block Diagram Intel 80219 General Purpose PCI ProcessorIntroduction Summary of Features Intel IQ80219 Evaluation Platform Board FeaturesFeature Definition First-Time Installation and Test Kit ContentHardware Installation Power and Backplane RequirementsDevelopment Strategy Factory SettingsContents of the Flash Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightGetting Started Connecting with GDB GDB set remotebaudARM Extended Debugger This Page Left Intentionally Blank Giga Ethernet Functional DiagramIntel fi BridgeForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesMemory Subsystem Battery BackupDDR Memory Features Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode Interrupt Routing IQ80219 Interrupt routingPeripheral Bus Features Intel IQ80219 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsEthernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 DescriptionsSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9E1 Jumper J9F1This Page Left Intentionally Blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceComponents on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Software Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80219 General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel General Purpose PCI Processor Memory Map Redboot* Intel IQ80219 Memory Map Physical Address Range DescriptionRedboot Intel IQ80219 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80219 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Purpose IntroductionNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping