Intel IQ80219 manual Hex Display Connection to Peripheral Bus

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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Software Reference

5.2.4HEX Display

The HEX Display is an Agilent* HDSP-G211, which allows for monitoring of two digits. It sits on the Peripheral Bus and is accessed using PCE2 and PCE3 as shown here:

Figure 21. Hex Display Connection to Peripheral Bus

Agilent*

HDSP-G211

Hex Display

Intel® 80219

General Purpose

PCI Processor

PCE3

PCE2

Intel® 80219 General Purpose PCI

Processor Peripheral Bus

* Other names and brands may be claimed as property of others.

B2833-01

Redboot* uses address range 0xFE84 0000 - 0xFE84 0FFF for the left 7-segment LED (PCE3) and address range 0xFE85 0000 - 0xFE85 0FFF for the right 7-segment LED (PCE2).

Figure 22. 7-Segment Display Bit Definition

Figure 23. Register Bitmap: 7-Segment Display MSB FE84 0000h (Write Only)

74	Board Manual

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Contents Board Manual November 13Board Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Rstmode and Retry Operation Setting Summary Tables105 Revision History Date Revision DescriptionThis Page Left Intentionally Blank Document Purpose and Scope Related DocumentsElectronic Information Electronic InformationComponent References Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80219 General Purpose PCI Processor Block Diagram Intel 80219 General Purpose PCI ProcessorIntroduction Feature Definition Intel IQ80219 Evaluation Platform Board FeaturesSummary of Features First-Time Installation and Test Kit ContentHardware Installation Power and Backplane RequirementsDevelopment Strategy Factory SettingsContents of the Flash Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightGetting Started Connecting with GDB GDB set remotebaudARM Extended Debugger This Page Left Intentionally Blank Giga Ethernet Functional DiagramIntel ﬁ BridgeForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesMemory Subsystem Battery BackupDDR Memory Features Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode Interrupt Routing IQ80219 Interrupt routingPeripheral Bus Features Intel IQ80219 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsEthernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Mictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 DescriptionsSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9E1 Jumper J9F1This Page Left Intentionally Blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Software Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel 80219 General Purpose PCI Processor Memory Map Redboot* Intel IQ80219 Memory Map Physical Address Range DescriptionRedboot Intel IQ80219 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80219 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Necessary Hardware and Software IntroductionPurpose Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping