Intel IQ80219 manual Registers Window, Watch Window, Variables Window

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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Getting Started and Debugger

B.8.6 Registers Window

Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. This is useful for seeing the system flags defined by the CPSR. These are important especially during conditional code execution (see the ARM Architecture Reference Manual for more detail), but the flags are not changed during this exercise.

Click on the registers tab of the registers window and click the Animate icon. Notice how the register values change during program execution (red values are those that were modified during the last execution cycle). Click the Halt icon at any time, then try right clicking a register row and selecting “Go To Memory”. Notice how the Memory window is brought up and the address contained in that register is shown.

Click on the registers tab. Red means that the register value changed since the last fetch as opposed to black which represents no change. Register values can be manually changed in this window.

B.8.7 Watch Window

It is often useful during the debugging process to keep an eye on a few select program variables.

1.Open the Tester1LED Program and bring up “led.c”.

2.Click the “Watch” icon to bring up the Watch window.

3.Now add the “left” and “right” variables from “led.c” to the watch window.

Note: For each variable double click the variable name to highlight it, then drag it to the watch window.

4. Click the “Animate” icon and observe the changes.

Note: When focus goes back to the Assembly window during this process, try putting a breakpoint in led.c, then hit Go.

B.8.8 Variables Window

The Variables behaves very similarly to the Watch window, except that simply shows all active variables. Bring up the Variables window, click Animate, and watch the changes.

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Contents November 13 Board ManualBoard Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Tables Rstmode and Retry Operation Setting Summary105 Date Revision Description Revision HistoryThis Page Left Intentionally Blank Related Documents Document Purpose and ScopeComponent References Electronic InformationElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80219 General Purpose PCI Processor Intel 80219 General Purpose PCI Processor Block DiagramIntroduction Feature Definition Intel IQ80219 Evaluation Platform Board FeaturesSummary of Features Hardware Installation Kit ContentFirst-Time Installation and Test Power and Backplane RequirementsContents of the Flash Factory SettingsDevelopment Strategy Supported Tool BucketsTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootGetting Started GDB set remotebaud Connecting with GDBARM Extended Debugger This Page Left Intentionally Blank Intel fi Functional DiagramGiga Ethernet BridgeBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerDDR Memory Features Battery BackupMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode IQ80219 Interrupt routing Interrupt RoutingIntel IQ80219 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusConsole Serial Port Debug InterfaceEthernet Port Intel 82544EI Gigabit Ethernet ControllerJtag Debug Logic-Analyzer Connectors3.1 Jtag Port Jtag Port Pin-outMictor J3F2 Micor J3F2 Signal/PinsMictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Requirements/Schemes Board Reset SchemeSwitch Summary Switches and JumpersPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5Switch S7E1 8 Descriptions Switch S7E1Switch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Settings and Operation Mode Switch S8E1 5 DescriptionsSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 Switch S8E2 1/2Switch S9E1 13 Descriptions Switch S9E1Switch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9F1 Jumper J9E1This Page Left Intentionally Blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationDDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Software Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel 80219 General Purpose PCI Processor Memory Map Physical Address Range Description Redboot* Intel IQ80219 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80219 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80219 Virtual Memory Map VisualRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Necessary Hardware and Software IntroductionPurpose Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping