Intel IQ80219 manual Using Flash Programmer

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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Getting Started and Debugger

B.4.2 Using Flash Programmer

Note: The parallel port must be set to EPP mode or the Macraigor Raven will not work properly.

Download the RedBoot executable files from the following location:

http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ8032/IQ80219 boards

1.Double click on the “CodeLab Debug” icon on the desktop. The Connection Window appears.

2.Select Macraigor JTAG Connect a. click Setup.

3.Select “ARM XScale”, correct LPT port, and “Raven” (do not press OK).

4.Click Additional Options…, check Enable Option, then press Configure The Console Options windows now appears.

5.Console Port: (Set appropriately)

Baud Rate: 115200

Data Bits: 8

Parity: None

Stop Bits: 1

Then Press OK,OK, OK (this returns to the Connect window).

6.Now press Connect. Assembly code now visible.

7.Select “Memory/Flash…”

The OCDemon Flash Memory Programmer window appears.

8.The Flash programmer needs a file which is architecture specific, in this case. In the Flash programmer window, select “File/Open”, then choose the file “XscaleVerde.ocd” at”C:\ATI\codelab\codelab Debug\Macraigor\”.

9.Click the Program button.

10.Click Browse and “Files of type:” All Files, then choose the “redboot_ROM.srec” file (downloaded http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ80321/IQ80219 boards and uncompressed from developer.com).

11.Check box “Erase Target Flash Sector(s) Before Programming”.

12.Click OK

The Flash now programs and verifies; click Close when 100% complete.

13.Cycle power to the board to see that the LEDs on the board sequence “8.8.”, “A5”, “A6”, “S.L”, then “A1”.

This is the normal LED sequence of RedBoot. The board may need to be reset more than once.

Explore the other features of the Flash programming window. The contents of the Flash can be erased, copied to a file on the host, and verified against a file on the host.

94	Board Manual

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Contents Board Manual November 13Board Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Rstmode and Retry Operation Setting Summary Tables105 Revision History Date Revision DescriptionThis Page Left Intentionally Blank Document Purpose and Scope Related DocumentsElectronic Information Electronic InformationComponent References Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80219 General Purpose PCI Processor Block Diagram Intel 80219 General Purpose PCI ProcessorIntroduction Summary of Features Intel IQ80219 Evaluation Platform Board FeaturesFeature Definition First-Time Installation and Test Kit ContentHardware Installation Power and Backplane RequirementsDevelopment Strategy Factory SettingsContents of the Flash Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightGetting Started Connecting with GDB GDB set remotebaudARM Extended Debugger This Page Left Intentionally Blank Giga Ethernet Functional DiagramIntel ﬁ BridgeForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesMemory Subsystem Battery BackupDDR Memory Features Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode Interrupt Routing IQ80219 Interrupt routingPeripheral Bus Features Intel IQ80219 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsEthernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 DescriptionsSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9E1 Jumper J9F1This Page Left Intentionally Blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceComponents on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Software Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80219 General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel General Purpose PCI Processor Memory Map Redboot* Intel IQ80219 Memory Map Physical Address Range DescriptionRedboot Intel IQ80219 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80219 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Purpose IntroductionNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping