Intel IQ80219 manual Jumper J9E1, Jumper J9F1

Page 67

Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Hardware Reference Section

3.10.9.22Jumper J9E1

Base Address Register Enable:

Used to enable the base address register at reset or power-up. The 64-bit register located at offsets x'10' and x'14' is used to claim a 1 MB memory region when enabled. The register returns all zeroes to read accesses and the associated memory region is not claimed when disabled.

0 = (1-2): BAR disabled, register reads returns 0s, no memory region claimed.

1 = (2-3): BAR enabled, bits 63:20 can be written by software to claim a 1 MB memory region.

Table 82.

Jumper J9E1: Descriptions

 

 

 

 

 

 

 

 

Jumper

Association

Description

Factory Default

 

 

 

 

 

 

J9E1

PCI-X Bridge

BAR_EN: Enables Base Address Register (BAR)

2-3

 

 

 

 

 

Table 83.

Jumper J9E1: Settings and Operation Mode

 

 

 

 

 

 

 

J9E1

 

Operation Mode

 

 

 

 

 

Pins 1,2

Pulled up. BAR disabled, register reads return 0s, no memory region claimed.

 

 

 

 

Pins 2,3

Pulled down. BAR enabled, bits 63:20 can be written by software to claim a 1 MB memory

 

region.

 

 

 

 

 

 

 

 

 

 

 

3.10.9.23Jumper J9F1

Primary Configuration Busy:

Controls the reset and power up value of bit 2 of the miscellaneous control register. Used to sequence initialization with regard to the primary and secondary buses for applications that require access to the bridge configuration registers from the secondary bus. When pulled high, the configuration commands received on the primary bus are retried until such time as bit 2 of the miscellaneous control register is set to b‘0’ by a configuration write initiated from the secondary bus. Applications that do not require access to the bridge configuration registers from the secondary bus pull this signal to ground.

0 = (2-3): Reset value of bit 2 of the miscellaneous control register is b‘0’.

1 = (1-2): Reset value of bit 2 of the miscellaneous control register is b‘1’.

Table 84.

Jumper J9F1: Descriptions

 

 

 

 

 

 

 

 

Jumper

Association

Description

Factory Default

 

 

 

 

 

 

J9F1

PCI-X Bridge

P_CFG_BUSY: Allows user to control initialization

2-3

 

sequence on the bridge.

 

 

 

 

 

 

 

 

 

Table 85.

Jumper J9F1: Settings and Operation Mode

 

J9F1

Operation Mode

 

 

 

 

Pins 1,2

Pulled up. Reset value of bit 2 of the miscellaneous control register to b’0’.

 

 

 

 

Pins 2,3

Pulled down. Reset value of bit 2 of the miscellaneous control register to b’1’.

 

 

 

Board Manual

67

Image 67
Contents November 13 Board ManualBoard Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Tables Rstmode and Retry Operation Setting Summary105 Date Revision Description Revision HistoryThis Page Left Intentionally Blank Related Documents Document Purpose and ScopeComponent Reference Electronic InformationComponent References Electronic InformationTerms and Definitions Terms and DefinitionsDefinition Intel 80219 General Purpose PCI Processor Intel 80219 General Purpose PCI Processor Block DiagramIntroduction Summary of Features Intel IQ80219 Evaluation Platform Board FeaturesFeature Definition Power and Backplane Requirements Kit ContentHardware Installation First-Time Installation and TestSupported Tool Buckets Factory SettingsContents of the Flash Development StrategyTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootGetting Started GDB set remotebaud Connecting with GDBARM Extended Debugger This Page Left Intentionally Blank Bridge Functional DiagramIntel fi Giga EthernetBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerSupported Dimm Types Battery BackupDDR Memory Features Memory SubsystemFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode IQ80219 Interrupt routing Interrupt RoutingIntel IQ80219 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusIntel 82544EI Gigabit Ethernet Controller Debug InterfaceConsole Serial Port Ethernet PortJtag Port Pin-out Logic-Analyzer ConnectorsJtag Debug 3.1 Jtag PortMictor J3F2 Micor J3F2 Signal/PinsSchematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Requirements/Schemes Board Reset SchemeSwitch Summary Switches and JumpersPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5S7E1-8 Switch S7E1Switch S7E1 8 Descriptions Switch S7E1 8 Settings and Operation ModeSwitch S8E1 Switch S8E1 6 Descriptions Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 5 Driver Mode Output ImpedancesSwitch S8E1 8 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 DescriptionsSwitch S8E2 Switch S8E2 1/2Switch S9E1 4 Descriptions Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 13 Settings and Operation ModeSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9F1 Jumper J9E1This Page Left Intentionally Blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationComponents on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Software Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80219 General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel General Purpose PCI Processor Memory Map Physical Address Range Description Redboot* Intel IQ80219 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80219 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80219 Virtual Memory Map VisualRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Purpose IntroductionNecessary Hardware and Software Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Hardware Breakpoints Debugging BasicsHardware and Software Breakpoints Software BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping