Intel IQ80219 manual Pcix Initialization Summary, User Defined Switches

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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform

Hardware Reference Section

3.10.2PCIX Initialization Summary

Figure 16 shows a routing guidance on how PCI-X mode is determined/implemented on the secondary side of the PCI-X bridge. The 80219, GbE device, and the PCI-X expansion slot all reside on this bus.

Figure 16. PCI-X Routing Diagram on Secondary PCI-X Bridge

 

Switch

 

 

Switch

 

 

Switch

 

S8E1-4

 

 

 

S7E1-8

 

 

 

S7E1-6

S7E1-7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sel 100

 

 

Enable

 

 

Selection

 

 

 

 

 

 

 

 

 

 

33 MHz

66 MHz

100 MHz

133 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI-X

 

 

 

 

 

Clock

 

 

 

Bridge

 

 

 

Multiplier/Bufferr

 

 

 

 

 

PCI-X Clock

 

 

 

 

 

 

 

 

 

 

 

PCIXCAP

 

 

 

 

 

 

 

 

 

 

 

M66EN Signal

 

 

 

 

 

 

 

 

 

 

 

S_DEVSEL

 

 

 

 

 

 

 

 

Initialization Signals

 

S_TRDY

 

 

 

 

 

 

 

 

 

 

 

S_FRAME

 

 

 

 

 

 

 

 

 

 

 

S_IRDY

 

 

 

 

 

 

 

 

 

 

 

S_STOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switch

S8E2-1 S8E2-2

PCIXCAP

OSC

Switch

S8E2-4

M66EN

SPCI-X Slot

Intel® 80219

General

Purpose

PCI

Processor

82544

Gigabit Ethernet

B2840-01

3.10.2.1User Defined Switches

User can set the PCIXCAP signal to force one of the following modes:

PCI-X 100/133

PCI-X 66

PCI

The IQ80219 platform is by default set to operate this bus in PCI-X 66 MHz mode. The loading on the secondary PCI-X bus may result in marginal operation when speed is greater than that.

When an expansion card is placed on the PCI-X expansion slot, the mode is based on the least capable device on the bus. For example, when the bus is forced to be PCI-X 66 capable and then places a PCI 66 card in the expansion slot, then the bus is configured as PCI 66.

Important: The clock selection is manually configured. Pay close attention to setting this up correctly.

Important: All settings must be done prior to power-up/reset.

3.10.2.2PCI-X Bridge Initialization Signals

The On-board PCI-X bridge samples the PCIXCAP, SEL100, and M66EN signals to drive/indicate the correct mode to the secondary bus devices. The 80219 uses these signals to set its internal PLs, providing correct frequency to the Intel XScale® core, as well as internal, peripheral, and DDR buses.

Board Manual

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Contents November 13 Board ManualBoard Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Tables Rstmode and Retry Operation Setting Summary105 Date Revision Description Revision HistoryThis Page Left Intentionally Blank Related Documents Document Purpose and ScopeComponent References Electronic InformationElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80219 General Purpose PCI Processor Intel 80219 General Purpose PCI Processor Block DiagramIntroduction Feature Definition Intel IQ80219 Evaluation Platform Board FeaturesSummary of Features Hardware Installation Kit ContentFirst-Time Installation and Test Power and Backplane RequirementsContents of the Flash Factory SettingsDevelopment Strategy Supported Tool BucketsTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootGetting Started GDB set remotebaud Connecting with GDBARM Extended Debugger This Page Left Intentionally Blank Intel fi Functional DiagramGiga Ethernet BridgeBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerDDR Memory Features Battery BackupMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80219 General Purpose PCI Processor Operation Mode IQ80219 Interrupt routing Interrupt RoutingIntel IQ80219 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusConsole Serial Port Debug InterfaceEthernet Port Intel 82544EI Gigabit Ethernet ControllerJtag Debug Logic-Analyzer Connectors3.1 Jtag Port Jtag Port Pin-outMictor J3F2 Micor J3F2 Signal/PinsMictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Requirements/Schemes Board Reset SchemeSwitch Summary Switches and JumpersPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5Switch S7E1 8 Descriptions Switch S7E1Switch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Settings and Operation Mode Switch S8E1 5 DescriptionsSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 Switch S8E2 1/2Switch S9E1 13 Descriptions Switch S9E1Switch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9F1 Jumper J9E1This Page Left Intentionally Blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationDDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Software Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel 80219 General Purpose PCI Processor Memory Map Physical Address Range Description Redboot* Intel IQ80219 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80219 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80219 Virtual Memory Map VisualRedboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Necessary Hardware and Software IntroductionPurpose Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping