Intel IQ80960RM, RN manual Primary PCI Interface Initialization, Primary ATU Initialization

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MON960 Support for IQ80960RM/RN

5.2.5Primary PCI Interface Initialization

The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two functions (from a PCI Configuration Space standpoint) are supported.

•Function 0 is the PCI-to-PCI Bridge of the i960 RM/RN I/O processor, which optionally provides access capability between the primary PCI bus and the secondary PCI bus.

•Function 1 is the Primary ATU which provides access capability between the primary PCI bus and the local i960 bus.

The platform can be initialized into one of four modes. Modes 0 and 3 are described below.

Table 5-1.

Initialization Modes

 

 

 

 

 

 

 

 

 

 

RST_MODE#/

RETRY/

Initialization

Primary PCI Interface

i960 Core

 

SW1-1

SW1-2

Mode

Processor

 

 

 

 

 

 

 

 

 

0/ON

0/ON

Mode 0

Accepts Transactions

Held in Reset

 

 

 

 

 

 

 

0/ON

1/OFF

Mode 1

Retries All Configuration Transactions

Held in Reset

 

 

 

 

 

 

 

1/OFF

0/ON

Mode 2

Accepts Transactions

Initializes

 

 

 

 

 

 

 

1/OFF

1/OFF

Mode 3 (default)

Retries All Configuration Transactions

Initializes

 

 

 

 

 

 

When the IQ80960RM/RN is operating in Mode 0, the processor core is held in reset, allowing register defaults to be used on the Primary PCI interface. This mode is used to program the onboard Flash with either IxWORKS* or MON960.

When the IQ80960RM/RN platform is operating in Mode 3, the Configuration Cycle Disable bit in the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this mode, the IQ80960RM/RN platform sends PCI Retries when the PCI host attempts to access the platform’s Configuration Space. This mode allows the IQ80960RM/RN processor time to initialize its internal registers. The processor remains in this mode until the Configuration Cycle Disable bit in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI host problems, Primary PCI initialization occurs at the earliest possible opportunity after Memory and SDRAM controller initialization.

5.2.6Primary ATU Initialization

Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization by the PCI host processor. Local initialization occurs first and consists mainly of establishing the operational parameters for access to the local IQ80960RM/RN platform bus. The Primary Inbound ATU Limit Register (PIALR) is initialized to establish the block size of memory required by the Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary Inbound ATU Translate Value Register (PIATVR) is initialized to establish the translation value for PCI-to-Local accesses. The PIATVR value is set to reference the base of local SDRAM. The Primary Outbound Memory Window Value Register (POMWVR) is initialized to establish the translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map, which is typically occupied by PCI host memory. Likewise, the Primary Outbound I/O Window Value Register (POIOWVR) remains at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also established to allow for communication between the IQ80960RM/RN platform and a PCI bus master using the doorbell mechanism.

IQ80960RM/RN Evaluation Board Manual

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Contents Board Manual IQ80960RM/RN Evaluation PlatformIQ80960RM/RN Evaluation Platform Board Manual Contents 2.1 Tables FiguresPage Introduction IQ80960RM/IQ80960RN Platform Functional Block DiagramIQ80960RN Platform Physical Diagram Software Development Tools I960 RM/RN I/O Processor and IQ80960RM/RN FeaturesIxWorks* Real-Time Operating System Tornado* for I20* Software Development ToolsetTornado Build Tools Tornado Test and Debug ToolsCtools and the MON960 Debug Monitor Ctools Software Development ToolsetSPI610 Jtag Emulation System About This Manual Brief description of the contents of this manual followsTechnical Support Notational-ConventionsCountry Literature Customer Support Number Intel Customer Electronic Mail SupportIntel Customer Support Contacts Document Information Related InformationCyclone Contacts Product Document Name Company/ Order #Page Software Installation Pre-Installation ConsiderationsInstalling Software Development Tools Getting StartedBattery Backup Hardware InstallationInstalling the IQ80960RM/RN Platforms in the Host System Verify IQ80960RM/RN Platform is FunctionalCreating and Downloading Executable Files Sample Download and Execution Using GDB960Page IQ80960RN Platform Power Requirements Power RequirementsIQ80960RM Platform Power Requirements Hardware ReferenceTable Clocks Sdram PerformanceSdram Performance Flash ROM Sdram ConfigurationsUpgrading Sdram Flash ROM ProgrammingPCI Slots Power Availability Secondary PCI Bus Expansion ConnectorsConsole Serial Port Uart Register AddressesLoss of Fan Detect Battery BackupInterrupt and Idsel Routing Secondary PCI Bus Interrupt and Idsel RoutingJ12 J10 Logic Analyzer HeadersLogic Analyzer Header Definitions Jtag Header Switch S1 SettingsJtag Header Pinout PinUser LEDs During Initialization User LEDs10. Start-up LEDs MON960 LEDs Tests11. IQ80960RM/RN Connectors and LEDs Page I960 RM/RN I/O Processor Overview I960 RM/RN I/O Processor Block DiagramIQ80960RM/RN Platform Memory Map CPU Memory MapLocal Interrupts I960 RN/RM I/O Processor I960 RM/RN I/O Processor Interrupt Controller ConnectionsSecondary PCI Interface CPU Counter/TimersPrimary PCI Interface Application Accelerator Unit DMA ChannelsApplication Accelerator Unit Performance Monitor UnitPage 1 MON960 Initialization MON960 Support for IQ80960RM/RNMON960 Components Sdram Initialization 2 80960JT Core InitializationMemory Controller Initialization Primary ATU Initialization Primary PCI Interface InitializationInitialization Modes Initialization Primary PCI Interface I960 Core SW1-1 SW1-2Secondary ATU Initialization PCI-to-PCI Bridge InitializationSecondary PCI Initialization MON960 KernelMON960 Extensions SysPCIBIOSPresent PCI Bios RoutinesSysFindPCIDevice SysGenerateSpecialCycle SysReadConfigWord SysWriteConfigByte SysWriteConfigDword Additional MON960 Commands Diagnostics / Example CodeBoard Level Diagnostics Secondary PCI DiagnosticsQty Location Part Description Manufacturer Bill of MaterialsTable A-1. IQ80960RN Bill of Materials Sheet 1 Table A-1. IQ80960RN Bill of Materials Sheet 2 Location Part Description Manufacturer Table A-1. IQ80960RN Bill of Materials Sheet 3CR8 Table A-1. IQ80960RN Bill of Materials Sheet 4Table A-2. IQ80960RM Bill of Materials Sheet 1 Table A-2. IQ80960RM Bill of Materials Sheet 2 Table A-2. IQ80960RM Bill of Materials Sheet 3 Table A-2. IQ80960RM Bill of Materials Sheet 4 Part Description Manufacturer Table A-2. IQ80960RM Bill of Materials Sheet 5Bill of Materials Schematic Title SchematicsTable B-1. IQ80960RN Schematics List IC Decoupling Connpcia REV Memory Controller Dclkin Dramclk LA Spares Dramclkla Mictor SDRAM-DIMM168P RST# Jtag Header Spci Conn Inta A6 RNC4R8P SAD48 SPAR64 SREQ4# Spares Table B-2. IQ80960RM Schematics List 80960RM REV Primary PCI Interface RCE1# RWE# Outb RAD16 TXD SBA0 DQ0 SCB0 SCE1# DQ2 SAD2 AD3S CONNPCI32 Trst A1 SINTD# B7 Intb Intc A7 SINTA# PALLV16V8-10JC Page Chip PALLV16V8Z-20JI PLD CodePage Recycling the Battery

RN, IQ80960RM specifications

The Intel IQ80960RM and RN are part of the Intel i960 family of microprocessors, which were specifically designed for embedded applications in real-time computing environments. Introduced in the early 1990s, these processors were aimed at providing high-performance processing capabilities in industrial, telecommunications, and military systems.

One of the key features of the IQ80960RM and RN is their ability to support a 32-bit architecture, delivering a significant performance advantage over 16-bit and earlier processors. This architecture enables the execution of complex algorithms and the management of large amounts of data, making these microprocessors suitable for demanding applications.

The i960 family is built around a superscalar architecture, allowing multiple instructions to be completed in a single clock cycle. This is achieved through advanced instruction pipelining, which significantly boosts throughput and overall computational speed. The IQ80960RM and RN also included features like branch prediction and out-of-order execution, enhancing efficiency and reducing latency in real-time applications.

Memory management capabilities are another strong point of the IQ80960RM and RN. They support both virtual and physical memory addressing, enabling sophisticated memory management strategies. Their integrated memory management unit (MMU) allows for easier and more effective memory allocation, critical for real-time operating systems that require precise timing and resource management.

Furthermore, these processors are designed with an extensive instruction set architecture (ISA), which supports a wide range of operations, including digital signal processing (DSP) tasks. This versatility allows them to be utilized in various applications, from automotive systems to robotics, where reliable performance is paramount.

The thermal performance and power efficiency of the IQ80960RM and RN has also been a notable characteristic. With operational capabilities across various temperature ranges, these chips are well-suited for harsh environments often found in industrial settings.

In terms of connectivity, the IQ80960 series supports multiple I/O interfaces and communication protocols, ensuring that they can integrate seamlessly with other components and systems. This flexibility enhances their usability in networked applications, particularly in embedded systems.

Overall, the Intel IQ80960RM and RN processors represent a significant step forward in embedded processor technology, characterized by their robust performance, advanced features, and ability to meet the stringent demands of real-time applications across various industries.
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