Intel RN, IQ80960RM manual PCI Bios Routines, SysPCIBIOSPresent

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MON960 Support for IQ80960RM/RN

5.4.2PCI BIOS Routines

MON960 includes PCI BIOS routines to aid application software initialization of the secondary PCI bus. The supported BIOS functions are described in the subsections that follow.

sysPCIBIOSPresent

sysFindPCIDevice

sysFINDPCIClassCode

sysGenerateSpecialCycle

sysReadConfigByte

sysReadConfigWord

sysReadConfigDword

sysWriteConfigByte

sysWriteConfigWord

sysWriteConfigDword

sysGetIrqRoutingOptions

sysSetPCIIrq

These functions preserve, as closely as possible, the parameters and return values described in the PCI Local Bus Specification Revision 2.1. Functions that return multiple values do so by filling in the fields of a structure passed by the calling routine.

You can access these functions via a calls instruction. The system call indices are defined in the MON960 source file PCI_BIOS.H. The function prototypes are defined in the IQRP_ASM.H file.

5.4.2.1sysPCIBIOSPresent

This function allows the caller to determine whether the PCI BIOS interface function set is present, and the current interface version level. It also provides information about the hardware mechanism used for accessing configuration space and whether or not the hardware supports generation of PCI Special Cycles.

Calling convention:

int sysPCIBIOSPresent (

PCI_BIOS_INFO *info

);

Return values:

This function always returns SUCCESSFUL.

5-6

IQ80960RM/RN Evaluation Board Manual

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Contents IQ80960RM/RN Evaluation Platform Board ManualIQ80960RM/RN Evaluation Platform Board Manual Contents 2.1 Figures TablesPage IQ80960RM/IQ80960RN Platform Functional Block Diagram IntroductionIQ80960RN Platform Physical Diagram I960 RM/RN I/O Processor and IQ80960RM/RN Features Software Development ToolsTornado* for I20* Software Development Toolset IxWorks* Real-Time Operating SystemTornado Build Tools Tornado Test and Debug ToolsCtools and the MON960 Debug Monitor Ctools Software Development ToolsetSPI610 Jtag Emulation System Brief description of the contents of this manual follows About This ManualNotational-Conventions Technical SupportCountry Literature Customer Support Number Intel Customer Electronic Mail SupportIntel Customer Support Contacts Related Information Document InformationCyclone Contacts Product Document Name Company/ Order #Page Pre-Installation Considerations Software InstallationInstalling Software Development Tools Getting StartedHardware Installation Battery BackupInstalling the IQ80960RM/RN Platforms in the Host System Verify IQ80960RM/RN Platform is FunctionalSample Download and Execution Using GDB960 Creating and Downloading Executable FilesPage Power Requirements IQ80960RN Platform Power RequirementsIQ80960RM Platform Power Requirements Hardware ReferenceTable Clocks Sdram PerformanceSdram Performance Sdram Configurations Flash ROMUpgrading Sdram Flash ROM ProgrammingSecondary PCI Bus Expansion Connectors PCI Slots Power AvailabilityConsole Serial Port Uart Register AddressesBattery Backup Loss of Fan DetectInterrupt and Idsel Routing Secondary PCI Bus Interrupt and Idsel RoutingJ12 J10 Logic Analyzer HeadersLogic Analyzer Header Definitions Switch S1 Settings Jtag HeaderJtag Header Pinout PinUser LEDs User LEDs During Initialization10. Start-up LEDs MON960 LEDs Tests11. IQ80960RM/RN Connectors and LEDs Page I960 RM/RN I/O Processor Block Diagram I960 RM/RN I/O Processor OverviewCPU Memory Map IQ80960RM/RN Platform Memory MapLocal Interrupts I960 RM/RN I/O Processor Interrupt Controller Connections I960 RN/RM I/O ProcessorSecondary PCI Interface CPU Counter/TimersPrimary PCI Interface DMA Channels Application Accelerator UnitPerformance Monitor Unit Application Accelerator UnitPage 1 MON960 Initialization MON960 Support for IQ80960RM/RNMON960 Components Sdram Initialization 2 80960JT Core InitializationMemory Controller Initialization Primary PCI Interface Initialization Primary ATU InitializationInitialization Modes Initialization Primary PCI Interface I960 Core SW1-1 SW1-2PCI-to-PCI Bridge Initialization Secondary ATU InitializationSecondary PCI Initialization MON960 KernelMON960 Extensions PCI Bios Routines SysPCIBIOSPresentSysFindPCIDevice SysGenerateSpecialCycle SysReadConfigWord SysWriteConfigByte SysWriteConfigDword Diagnostics / Example Code Additional MON960 CommandsBoard Level Diagnostics Secondary PCI DiagnosticsQty Location Part Description Manufacturer Bill of MaterialsTable A-1. IQ80960RN Bill of Materials Sheet 1 Table A-1. IQ80960RN Bill of Materials Sheet 2 Table A-1. IQ80960RN Bill of Materials Sheet 3 Location Part Description ManufacturerTable A-1. IQ80960RN Bill of Materials Sheet 4 CR8Table A-2. IQ80960RM Bill of Materials Sheet 1 Table A-2. IQ80960RM Bill of Materials Sheet 2 Table A-2. IQ80960RM Bill of Materials Sheet 3 Table A-2. IQ80960RM Bill of Materials Sheet 4 Table A-2. IQ80960RM Bill of Materials Sheet 5 Part Description ManufacturerBill of Materials Schematic Title SchematicsTable B-1. IQ80960RN Schematics List IC Decoupling Connpcia REV Memory Controller Dclkin Dramclk LA Spares Dramclkla Mictor SDRAM-DIMM168P RST# Jtag Header Spci Conn Inta A6 RNC4R8P SAD48 SPAR64 SREQ4# Spares Table B-2. IQ80960RM Schematics List 80960RM REV Primary PCI Interface RCE1# RWE# Outb RAD16 TXD SBA0 DQ0 SCB0 SCE1# DQ2 SAD2 AD3S CONNPCI32 Trst A1 SINTD# B7 Intb Intc A7 SINTA# PALLV16V8-10JC Page PLD Code Chip PALLV16V8Z-20JIPage Recycling the Battery

RN, IQ80960RM specifications

The Intel IQ80960RM and RN are part of the Intel i960 family of microprocessors, which were specifically designed for embedded applications in real-time computing environments. Introduced in the early 1990s, these processors were aimed at providing high-performance processing capabilities in industrial, telecommunications, and military systems.

One of the key features of the IQ80960RM and RN is their ability to support a 32-bit architecture, delivering a significant performance advantage over 16-bit and earlier processors. This architecture enables the execution of complex algorithms and the management of large amounts of data, making these microprocessors suitable for demanding applications.

The i960 family is built around a superscalar architecture, allowing multiple instructions to be completed in a single clock cycle. This is achieved through advanced instruction pipelining, which significantly boosts throughput and overall computational speed. The IQ80960RM and RN also included features like branch prediction and out-of-order execution, enhancing efficiency and reducing latency in real-time applications.

Memory management capabilities are another strong point of the IQ80960RM and RN. They support both virtual and physical memory addressing, enabling sophisticated memory management strategies. Their integrated memory management unit (MMU) allows for easier and more effective memory allocation, critical for real-time operating systems that require precise timing and resource management.

Furthermore, these processors are designed with an extensive instruction set architecture (ISA), which supports a wide range of operations, including digital signal processing (DSP) tasks. This versatility allows them to be utilized in various applications, from automotive systems to robotics, where reliable performance is paramount.

The thermal performance and power efficiency of the IQ80960RM and RN has also been a notable characteristic. With operational capabilities across various temperature ranges, these chips are well-suited for harsh environments often found in industrial settings.

In terms of connectivity, the IQ80960 series supports multiple I/O interfaces and communication protocols, ensuring that they can integrate seamlessly with other components and systems. This flexibility enhances their usability in networked applications, particularly in embedded systems.

Overall, the Intel IQ80960RM and RN processors represent a significant step forward in embedded processor technology, characterized by their robust performance, advanced features, and ability to meet the stringent demands of real-time applications across various industries.
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