Intel RN, IQ80960RM manual PCI-to-PCI Bridge Initialization, Secondary ATU Initialization

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MON960 Support for IQ80960RM/RN

By default, Primary Outbound Configuration Cycle parameters are not established. The ATU Configuration Register (ATUCR) is initialized to establish the operational parameters for the Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and secondary ATUs. The PCI host is responsible for allocating PCI address space (Memory, Memory Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.

5.2.7PCI-to-PCI Bridge Initialization

PCI-to-PCI Bridge initialization includes initialization by the 80960JT core and initialization by the PCI host processor. Local initialization occurs first and consists mainly of establishing the operational parameters for the secondary PCI interface of the PCI-to-PCI bridge. On the IQ80960RM/RN platform, the secondary PCI bus is configured to consist of private devices (not visible to PCI host configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register (SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted during conversion of PCI Type 1 configuration cycles on the primary PCI bus to PCI Type 0 configuration cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating transactions that will be forwarded to the primary PCI interface. The PCI host is responsible for assigning and initializing the PCI bus numbers, allocating PCI address space (Memory, Memory Mapped I/O, and I/O), and assigning the IRQ numbers to valid interrupt routing values.

5.2.8Secondary ATU Initialization

Secondary ATU (Bridge) initialization consists mainly of establishing the operational parameters for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention, the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the block size of memory required by the secondary ATU. The SIALR value is based on the installed SDRAM configuration. The Secondary Inbound ATU Translate Value Register (SIATVR) is initialized to establish the translation value for Secondary PCI-to-Local accesses. The SIATVR value is set to reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register (SOMWVR) is initialized to establish the translation value for Local-to-Secondary PCI accesses. The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window Value Register (SOIOWVR) is left at its default value of “0” to allow the IQ80960RM/RN platform to access the start of the PCI I/O address map.

On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as such, is required to configure the devices of the secondary PCI bus. Secondary Outbound Configuration Cycle parameters are established during secondary PCI bus configuration. Secondary PCI bus configuration is accomplished via MON960 Extension routines.

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IQ80960RM/RN Evaluation Board Manual

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Contents IQ80960RM/RN Evaluation Platform Board ManualIQ80960RM/RN Evaluation Platform Board Manual Contents 2.1 Figures TablesPage IQ80960RM/IQ80960RN Platform Functional Block Diagram IntroductionIQ80960RN Platform Physical Diagram I960 RM/RN I/O Processor and IQ80960RM/RN Features Software Development ToolsTornado Build Tools Tornado* for I20* Software Development ToolsetIxWorks* Real-Time Operating System Tornado Test and Debug ToolsCtools Software Development Toolset SPI610 Jtag Emulation SystemCtools and the MON960 Debug Monitor Brief description of the contents of this manual follows About This ManualNotational-Conventions Technical SupportIntel Customer Electronic Mail Support Intel Customer Support ContactsCountry Literature Customer Support Number Cyclone Contacts Related InformationDocument Information Product Document Name Company/ Order #Page Installing Software Development Tools Pre-Installation ConsiderationsSoftware Installation Getting StartedInstalling the IQ80960RM/RN Platforms in the Host System Hardware InstallationBattery Backup Verify IQ80960RM/RN Platform is FunctionalSample Download and Execution Using GDB960 Creating and Downloading Executable FilesPage IQ80960RM Platform Power Requirements Power RequirementsIQ80960RN Platform Power Requirements Hardware ReferenceSdram Performance Sdram PerformanceTable Clocks Upgrading Sdram Sdram ConfigurationsFlash ROM Flash ROM ProgrammingConsole Serial Port Secondary PCI Bus Expansion ConnectorsPCI Slots Power Availability Uart Register AddressesInterrupt and Idsel Routing Battery BackupLoss of Fan Detect Secondary PCI Bus Interrupt and Idsel RoutingLogic Analyzer Headers Logic Analyzer Header DefinitionsJ12 J10 Jtag Header Pinout Switch S1 SettingsJtag Header Pin10. Start-up LEDs MON960 User LEDsUser LEDs During Initialization LEDs Tests11. IQ80960RM/RN Connectors and LEDs Page I960 RM/RN I/O Processor Block Diagram I960 RM/RN I/O Processor OverviewCPU Memory Map IQ80960RM/RN Platform Memory MapLocal Interrupts I960 RM/RN I/O Processor Interrupt Controller Connections I960 RN/RM I/O ProcessorCPU Counter/Timers Primary PCI InterfaceSecondary PCI Interface DMA Channels Application Accelerator UnitPerformance Monitor Unit Application Accelerator UnitPage MON960 Support for IQ80960RM/RN MON960 Components1 MON960 Initialization 2 80960JT Core Initialization Memory Controller InitializationSdram Initialization Initialization Modes Primary PCI Interface InitializationPrimary ATU Initialization Initialization Primary PCI Interface I960 Core SW1-1 SW1-2PCI-to-PCI Bridge Initialization Secondary ATU InitializationMON960 Kernel MON960 ExtensionsSecondary PCI Initialization PCI Bios Routines SysPCIBIOSPresentSysFindPCIDevice SysGenerateSpecialCycle SysReadConfigWord SysWriteConfigByte SysWriteConfigDword Board Level Diagnostics Diagnostics / Example CodeAdditional MON960 Commands Secondary PCI DiagnosticsBill of Materials Table A-1. IQ80960RN Bill of Materials Sheet 1Qty Location Part Description Manufacturer Table A-1. IQ80960RN Bill of Materials Sheet 2 Table A-1. IQ80960RN Bill of Materials Sheet 3 Location Part Description ManufacturerTable A-1. IQ80960RN Bill of Materials Sheet 4 CR8Table A-2. IQ80960RM Bill of Materials Sheet 1 Table A-2. IQ80960RM Bill of Materials Sheet 2 Table A-2. IQ80960RM Bill of Materials Sheet 3 Table A-2. IQ80960RM Bill of Materials Sheet 4 Table A-2. IQ80960RM Bill of Materials Sheet 5 Part Description ManufacturerBill of Materials Schematics Table B-1. IQ80960RN Schematics ListSchematic Title IC Decoupling Connpcia REV Memory Controller Dclkin Dramclk LA Spares Dramclkla Mictor SDRAM-DIMM168P RST# Jtag Header Spci Conn Inta A6 RNC4R8P SAD48 SPAR64 SREQ4# Spares Table B-2. IQ80960RM Schematics List 80960RM REV Primary PCI Interface RCE1# RWE# Outb RAD16 TXD SBA0 DQ0 SCB0 SCE1# DQ2 SAD2 AD3S CONNPCI32 Trst A1 SINTD# B7 Intb Intc A7 SINTA# PALLV16V8-10JC Page PLD Code Chip PALLV16V8Z-20JIPage Recycling the Battery

RN, IQ80960RM specifications

The Intel IQ80960RM and RN are part of the Intel i960 family of microprocessors, which were specifically designed for embedded applications in real-time computing environments. Introduced in the early 1990s, these processors were aimed at providing high-performance processing capabilities in industrial, telecommunications, and military systems.

One of the key features of the IQ80960RM and RN is their ability to support a 32-bit architecture, delivering a significant performance advantage over 16-bit and earlier processors. This architecture enables the execution of complex algorithms and the management of large amounts of data, making these microprocessors suitable for demanding applications.

The i960 family is built around a superscalar architecture, allowing multiple instructions to be completed in a single clock cycle. This is achieved through advanced instruction pipelining, which significantly boosts throughput and overall computational speed. The IQ80960RM and RN also included features like branch prediction and out-of-order execution, enhancing efficiency and reducing latency in real-time applications.

Memory management capabilities are another strong point of the IQ80960RM and RN. They support both virtual and physical memory addressing, enabling sophisticated memory management strategies. Their integrated memory management unit (MMU) allows for easier and more effective memory allocation, critical for real-time operating systems that require precise timing and resource management.

Furthermore, these processors are designed with an extensive instruction set architecture (ISA), which supports a wide range of operations, including digital signal processing (DSP) tasks. This versatility allows them to be utilized in various applications, from automotive systems to robotics, where reliable performance is paramount.

The thermal performance and power efficiency of the IQ80960RM and RN has also been a notable characteristic. With operational capabilities across various temperature ranges, these chips are well-suited for harsh environments often found in industrial settings.

In terms of connectivity, the IQ80960 series supports multiple I/O interfaces and communication protocols, ensuring that they can integrate seamlessly with other components and systems. This flexibility enhances their usability in networked applications, particularly in embedded systems.

Overall, the Intel IQ80960RM and RN processors represent a significant step forward in embedded processor technology, characterized by their robust performance, advanced features, and ability to meet the stringent demands of real-time applications across various industries.
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