Intel 8080 manual Status Bit Definitions, Status Information Definition, Status Word Chart

Page 20

Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status informatton on the data bus at the beginning of each machine cycle (during SYNC time). The following table defines the status information.

 

STATUS INFORMATION DEFINITION

Symbols

Data Bus

 

Bit

Definition

INTA*

00

Acknowledge signal for INTERRUPT re-

 

 

quest. Signal should be used to gate a re-

 

 

start instruction onto the data bus when

 

 

OBIN is active.

 

0,

Indicates that the operation in the current

 

 

machine cycle will be a WR ITE memory

 

 

or OUTPUT function (WO = O).Otherwise,

 

 

a REAO memory or INPUT operation will

 

°2

be executed.

STACK

Indicates that the address bus holds the

 

pushdown stack address from the Stack

 

°3

Pointer.

HLTA

Acknowledge signal for HALT instruction.

°4

OUT

Indicates that the address bus contains the

 

address of an output device and the data

 

 

bus will contain the output data when

M,

°5

WR is active.

Provides a signal to indicate that the CPU

 

is in the fetch cycle for the first byte of

 

°6

an instruction.

INP*

Indicates that the address bus contains the

 

address of an input device and the input

 

 

data shou Id be placed on the data bus

 

 

when OB IN is active.

MEMR*

0 7

Designates that the data bus will be used

 

 

for memory read data.

*These three status bits can be used to control the flow of data onto the 8080 data bus.

STATUS WORD CHART

8080 STATUS LATCH

o10

o9

0,

o8

2 7

 

 

0 3

3

 

 

 

 

 

 

8080

0

4

4

 

 

 

 

 

 

0 5

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~6

6

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

SYNC -19

 

 

 

 

 

 

 

OBIN ~

 

 

 

 

 

 

01

02

 

 

 

 

STATUS

 

 

 

 

 

 

 

 

 

 

22

 

15

 

 

LATCH

 

 

 

 

--2. 0 1

 

 

 

 

 

 

 

 

 

 

DO

~ INTA

 

 

 

 

 

5

 

 

 

~ W6

 

 

 

 

 

~

 

 

 

~ STACK

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

~ HlTA

 

 

 

 

 

16

8212

 

.lL. OUT

 

 

 

 

 

18

 

 

 

 

 

 

 

17

M1

 

 

 

 

--

20

 

 

 

JL INP

CLOCK GEN.

 

 

22

 

 

 

 

 

(olTTl)

r;;

 

 

 

~ MEMR

 

 

 

 

~

 

I

I

 

 

 

 

 

 

 

OS2 MO

OS,

 

 

& DRIVER

 

 

 

 

CLR

 

 

 

 

 

 

 

 

 

 

13

12

Y1

 

 

DBIN

~

T2

01

SYNC

OATA 1------'' --- t -- t --

STATUS ......-.----+001'----1

TYPE OF MACHINE CYCLE

I

DO INTA

02STACK

03HLTA

04OUT

06 INP

07MEMR

Table 2-1. 8080 Status Bit Definitions

2-6

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Contents Page Clock Generator for 8080A System Controller for 8080AProgrammable Communication Interface Programmable Peripheral InterfaceContents Chapter Packaging Information 127Peri pherals Page Conventional System Programmed Logic Advantages of Designing With MicrocomputersMicrocomputer Design Aids 1IIII~Iff1 Applications ExampleIii Application Peripheral Devices EncounteredAccumulator Typical Computer SystemArchitecture of a CPU Program Counter Jumps, Subroutines and the Stack Instruction Register and DecoderControl Circuitry Address RegistersArithmetic/Logic Unit ALU Computer OperationsInstruction Fetch Memory ReadMemory Write Wait memory synchronizationPage Page INTE~ 8080 Photomicrograph With Pin DesignationsArchitecture of the 8080 CPU RegistersArithmetic and Logic Unit ALU Instruction Register and ControlData Bus Buffer Processor CycleMachine Cycle Identification State Transition Sequence HaltStatus Information Definition Status Word ChartStatus Bit Definitions CPU State Transition Diagram ?~~Rr\ ONE ,----- ~ State Associated Activities ~2. State DefinitionsRLrL- rL rL rL-rL- rLrL Interrupt Sequences¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL START-UP of the 8080 CPU Hold SequencesHalt Sequences 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~~11 ~iA~~ll,12~A~~~ll ~iA~~~11Value 111 000 001 010 011 100 101Typical Computer System Block Diagram Basic System OperationCPU Module Design 8080 CPUClock Generator and High Level Driver Clock Generator DesignHigh Level Driver Design ClK 0.......-..-.-----.. tf1A TTL~50ns Ststb !1 Page RAM Interface Interfacing the 8080 CPU to Memory and I/O DevicesROM Interface Ill Interface General TheoryIsolated I/O Memory Mapped I/OMemr to AddressingInterface Example 13 Format 15 FormatInstruction and Data Formats 8080 Instruction SETByte One Byte TwoByte Three I D7 Addressing ModesSymbols and Abbreviations Symbols MeaningDescription Format AllContent of register r2 is moved to register r1 Data Transfer GroupMOV r1, r2 Move Register Reg. indirect0 I R p 0 I R0 I Arithmetic Group1 I 0 I 0 oR 0 I 0 I D I DI I Logical GroupOCR M Decrement memory Cycles States Addressing reg. indirect Flags Z,S,P ,CY,ACI 0 I 1 I 1 I I 1 I 1 o I 1 I 1 I~11~ 1 1 10 I 1 I 0 I 0 1 I0 I 0 I Cycles States Flags noneBranch Group 000SP ~ SP + I c c I c I 0 I 0 ICcondition addr Stack, I/O, and Machine Control Group I 1 oPush rp 1 I RExchange stack top with Hand L ~ SP +~ data Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page Schottky Bipolar PIN NamesFunctional Description GeneralOscillator Clock GeneratorPower-On Reset and Ready Flip-Flops Ststb Status StrobeCharacteristics Crystal RequirementsInput 8pFCharacteristics For tCY = 488.28 ns ExampleT42 T01 T02 T03 Toss TORS tORH tOR FMAXPIN Configuration Block Diagram DbinGeneral BlockSignals Inta None ControlCharacteristics TA = Oc to 70C Vee = 5V ±5% TE~rWaveforms Hlda to Read Status OutputsGoUT StstbVTH VCC=5V·-c GND ---. rIntel Silicon Gate MOS 8080 a ?oo .H8080A Functional PIN Definition VeeVss Characteristics Absolute Maximum RATINGS·Capacitance IOl = 1.9mA on all outputs=..... -r-DATAIN ~I~~~Timing Waveforms ~~1 t CYCharacteristics Typical ~ Output Delay VS. a CapacitanceInstruction SET Typical InstructionsSilicon Gate MOS 8080.A Summary of Processor InstructionsInfel Silicon Gate MOS 8080A-1 Unit Symbol Parameter TypMax ~-t Fft~l~tOF.I TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 +10 CoutJ1A VAOOR/OATA = VSS + O.45VSymbol Parameter Min Unit Test ConditionTypical ~ Output Delay VS. ~ Capacitance Min. Max. Unit Test ConditionPage Intel . Silicon Gate MOS M8080A Immediate mode or I/O instructions Register to regist~r, memory referEnce, arithmetic or logical, rotate Interrupt instructionsSummary of Processor Instructions Llf17Silicon Gate MOS M8080A M8080A Functional PIN DefinitionOperation Absolute Maximum RatingsIOL = 1.9mA on all outputs Symbol Parameter Min. Max Unit Test Condition Silicon Gate MOS M8080A ~I~Page ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A Voo Operating CharacteristicsPIN Connections Switching Characteristics 1N= Vee~10% = V ce\ \ Cs=o.~Operating Characteristics for Programming Operation Symbol TestCharacteristics for Programming Operation SYMBOLTESTMIN. TYP. MAX. Unit ConditionsSwitching Characteristics for Programming Operation CS = OVProgramming Operation of the 8702A Program OperationOperation of the 8702A in Program Mode II. Programming of the 8702A Using Intel MicrocomputersIII a Erasing Procedure Programming Instructions for the 8702APage PIN Configurations Block Diagram PIN NamesComment IIIIBB VOH1Symbol Parameter Typ. Max. Unit Conditions Test ConditionsWaveforms Max UnitProgramming Current RnA Program Pulse Amplitude Parameter MinTpF Program Pulse Fall Time +-------1 Read/Program/Read TransitionsCS/WE = +12V 150 r PEEEf!1EJEZPlEzz$m=2!·m·· IccSilicon Gate MOS Comment MAX UnitCS=O.O Outa200ns 500ns 300 ns ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\100 ns 7001 JJ.s Typical Characteristics Cs .. o.~ ~rSilicon Gate MOS Ilcl IlpcIlkc ILOCIN Conditions of Test for CharacteristicsCoUT ~ ~ ~ Mask Option Specifications MarkingPppp Customer Number Oate~ r ------ + -- t --- . L . ------ rJ Title CardBlank 79-80PIN Configuration Block Diagram Intel Silicon Gate MOS ROM 8316ACAPACITANCE2 TA = 25C, f = 1 MHz 400Conditions of Test for OU~TVALID WaveformsTypical D.C. Characteristics ILICO.N Gate MOS ROM 8316ACustomer Number OateSTO Mask Option Speci FicationsTitle Card COM~ANY NameRAMs Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOS~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~= = OC10H = -150 p.A +----+Conditions of Test 00 ~Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOSSymbol Parameter Min. Typ.r IIIICC1 ICC2Write 1~-tAW--.I-----I 550 200Input Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level VoltPage Silicon Gate MOS Power Dissipation Watt 5V to +7VComment TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified85o-·-···T +--~~~TL~~~EEt~~~P-.±Capacitance T a = 25C, f = 1MHz Conditions of TestTypical A.C. Characteristics ~~~b~.JSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 300 450230 VIN Limits VS. Temperature Access Time VS Ambient TemperatureAccess Time VS LOAD·CAPACITANCE Output Source Current VSFully Decoded Random Access BIT Dynamic Memory PIN Configuration Logic Symbol Block DiagramSilicon Gate MOS 81078·4 IOOAV2II.~ IMP~ri~~CERead Cycle 4000Ref = Write CycleTypical Characteristics Numbers in parentheses are for minimum cycle timing in ns Symbol Parameter Min MaxRWc 590 CD Power Dissipation Standby PowerRefresh System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM ICC2 VIH VOL VOHVOR IcccrInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level Volt~I----- t CW2 ------ . t PIN Configuration Logic Symbol Schottky BipolarConditions of Test Voo- --- ---TPower Supply Current Drain and Power Dissipation All driver outputs are in the state indicatedTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page PIN Configuration Logic Diagram EIGHT-BIT INPUT/OUTPUT PortFunctional Description OS2Basic Schematic Symbols II. Gated Buffer 3·STATEAre 3-state Gated BufferIII. Bi-Directional Bus Driver IV. Interrupting Input PortInterrupt Instruction Port BI-DIRECTIONAL BUS DriverVI. Output Port With Hand-Shaking VII Status Latch8080 4 OvJ \.. -4~Viii System OUTVee SystemIX System DalN-t?!NrJ 1G~D L-~Characteristics Absolute Maximum Ratings·Typical Characteristics 052 ~OUT Tpw12 pF Switching CharacteristicsTA = OC to + 75C Vee = +5V ± 5% Programmable Peripheral Interface ~~~lEI~S 1-- +SVGeneral Data Bus BufferRead/Write and Control Logic Basic Functional DescriptionReset PIN ConfigurationGroup a and Group B Controls Ports A, B, and CMode Selection Single Bit Set/Reset FeatureDetailed Operational Description PA 7 ·pAoInterrupt Control Functions Operating Modes Mode 0 Basic Input/OutputMode 0 Timing Mode 0 Port Definition Chart Mode 0 Configurations119 Operating Modes Mode 1 Strobed Input/Output · / ,4Input Control Signal Definition IBF Input Buffer Full F/FIntr Interrupt Request Inte aOutput Control Signal Definition InteaCombinations of Mode Bi-Directional Bus I/O Control Signal DefinitionOperating Modes Output OperationsMode 2 Control Word Mode 2 Bi-directional TimingMode 2 Combinations Mode 2 and Mode 0 OutputSpecial Mode Combination Considerations Mode Definition Summary TableSource Current Capability on Port B and Port C Reading Port C StatusApplications Printer InterfaceKeyboard and Display Interface Keyboard and Terminal Address InterfacePCO ~.LEFT/RIGHTSilicon Gate MOS Characteristics TA = oc to 70C Vee = +5V ±5% vss = OV Vil Input Low VoltageInput High Voltage Val Output Low Voltage IOl = 1.6mA Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface Reset Reset GeneralReadlWrite Control logic ClK ClockModem Control DSR Data Set ReadyTxE Transmitter Empty DTR Data Termin·al ReadyReceiver Buffer Receiver ControlRxRDY Receiver Ready RxC Receiver ClockMode Instruction Command InstructionDetailed Operation Description ProgrammingMode Instruction Definition Asynchronous Mode TransmissionAsynchronous Mode Receive Data C~~RACTERSynchronous Mode Transmission Synchronous Mode ReceiveMode Instruction Format, Synchronous Mode Synchronous Mode, Transmission FormatCommand Instruction Definition Command Instruction FormatStatus Read Definition Status Read FormatAsynchronous Serial Interface to CRT Terminal, DC-9600 Baud Asynchronous Interface to Telephone LinesSynchronous Interface to Terminal or Peripheral Device Synchronous Interface to Telephone LinesIOL CapacitanceIcc TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter TypRxD SRX ~4IlI~AST BIT ,----1 RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder System Enable GateDecoder Using a very similar circuit to the I/O port decoder, an ar Port DecoderChip Select Decoder 24K Memory InterfaceLogic Element Example \lJJJ,.--+-I----.....1 IllCharacteristics TA = OOC to +75C, Vee = 5.0V ±5% Typical CharacteristicsSymbol VOL VOH 8205Switching Characteristics Conditions of Test Test Load Address or Enable to Output Delay VS. Load CapacitanceAddress or Enable to Output Delay VS. Ambient Temperature Test Waveforms~ ~ PIN Configuration~ R Interrupt Method Interrupts in Microcomputer SystemsPolled Method Priority Encoder Current Status RegisterControl Signals INTE, elKElR, ETlG, ENGl AO, A1, A2Level Controller Basic OperationI I Level ControllerCascading Operating Characteristics Symbol Parameter Limits Unit Conditions Min Typ.£1Los Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar +-......---- n cs 8216 8226Bi-Directional Driver Control Gating OlEN, CSLarge microcomputer systems it is often necessary to pro Applications of 8216/8226Memory and 1/0 Interface to a Bi-directional Bus IcC Power Supply Current 120 Input Load Current OlEN, CS VF =0.45Input Load Current All Other Inputs VF =0.45 Input Leakage Current OlEN, CS VR =5.25VWaveforms OUTPage 8253 8257 8259 Page Programmable Interval Timer It uses nMOS technology ~Jmodesof operation areBlock Diagram Preliminary Functional DescriptionSystem Interface System InterfaceProgrammable DMA Controller System Application System InterfaceDack 2 CS-------It LJJ CPU Group ROMs RAMsPeripheral Coming Soon IntelIt-j ~~~1735~ \.--.J.. ~~~l ·34o~Lead Plastic Dual IN-LINE Package P Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Instruction SET Summary of Processor Instructions By Alphabetical OrderMicrocomputer System Users Registration Card Intel Corporation Microcomputer Systems Bowers Avenue Santa Clara, CAInter
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8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.
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