Intel 8080 manual I 0 I 1 I 1 I, I 1 I 1 o I 1 I 1 I, ~11~, 1 1 1, Ora M

Page 53

ANI data (AND immediate)

(A) ~ (A) /\ (byte 2)

The content of the second byte of the instruction is logicaJly anded with the contents of the accumu lator . The result is placed in the accumulator. The CY and AC flags are cleared.

I 1 o I 0 I 1 I 1 I 0

data

Cycles: 2

States: 7

Addressing: immediate

Flags: Z,S,P ,CY ,AC

XRA r (Exclusive OR Register)

(A) ~ (A) V (r)

The content of register r is exclusive-or'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

Cycles: 1

States: 4

Addressing: register

Flags: Z,S,P,CY,AC

XRA M (Exclusive OR Memory)

(A) ~ (A) V ((H) (L))

The content of the memory location whose address is contained in the Hand L registers is exclusive-O R'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

I 0

o

I 0

 

Cycles:

2

 

States:

7

 

Addressing:

reg. indirect

 

Flags:

Z,S,P,CY,AC

XRI data (Exclusive OR immediate)

(A) ~ (A) V (byte 2)

The content of the second byte of the instruction is exclusive-O R'd with the content of the accumu lator. The result is placed in the accumulator. The CY and AC flags are cleared.

. 1~_1_1~

0 1--..1 ' _1__ 1 __ 0 _

 

 

1

1

.

data

 

 

 

Cycles:

2

 

 

States:

7

 

 

Addressing:

immediate

 

 

Flags:

Z,S,P ,CY ,AC

 

ORA r

(OR Register)

(A) ~ (A) V (r)

The content of register r is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

I 0 I

I 1

Cycles: 1

States: 4

Addressing: register

Flags: Z,S,P,CY,AC

ORA M

(OR memory)

(A) ~ (A) V ((H) (L))

The content of the memory location whose address is contained in the Hand L registers is inclusive-OR'd with the content of the accumu lator. The result is placed in the accumulator. The CY and AC flags are cleared.

I a I 1 I 1 o I 1 I 1 I 0

 

Cycles:

2

 

States:

7

 

Addressing:

reg. indirect

 

Flags:

Z,S,P ,CY ,AC

ORI data

(OR Immediate)

(A) ~ (A) V (byte 2)

 

The content of the second byte of the instruction is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

11

data

Cycles: 2

States: 7

Addressing: immediate

Flags: Z,S,P,CY,AC

CMP r (Compare Register)

(A)(r)

The content of register r is subtracted from the ac- cumulator. The accumulator remains unchanged. The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A) = (r). The CY flag is set to 1 if (A) < (r) .

I 0 I 1

Cycles: 1

States: 4

Addressing: register

Flags: Z,S,P,CY,AC

4-9

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Contents Page System Controller for 8080A Clock Generator for 8080AProgrammable Communication Interface Programmable Peripheral InterfaceContents Chapter Packaging Information 127Peri pherals Page Conventional System Programmed Logic Advantages of Designing With MicrocomputersMicrocomputer Design Aids 1IIII~Iff1 Applications ExampleIii Peripheral Devices Encountered ApplicationAccumulator Typical Computer SystemArchitecture of a CPU Instruction Register and Decoder Program Counter Jumps, Subroutines and the StackAddress Registers Control CircuitryArithmetic/Logic Unit ALU Computer OperationsMemory Read Instruction FetchMemory Write Wait memory synchronizationPage Page 8080 Photomicrograph With Pin Designations INTE~Registers Architecture of the 8080 CPUInstruction Register and Control Arithmetic and Logic Unit ALUData Bus Buffer Processor CycleMachine Cycle Identification Halt State Transition SequenceStatus Information Definition Status Word ChartStatus Bit Definitions ?~~ CPU State Transition DiagramRr\ ONE ,----- ~ ~2. State Definitions State Associated ActivitiesInterrupt Sequences RLrL- rL rL rL-rL- rLrL¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL START-UP of the 8080 CPU Hold SequencesHalt Sequences 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~ll,12 ~iA~~~11~A~~~ll ~iA~~~11111 000 001 010 011 100 101 ValueBasic System Operation Typical Computer System Block Diagram8080 CPU CPU Module DesignClock Generator and High Level Driver Clock Generator DesignHigh Level Driver Design ClK 0.......-..-.-----.. tf1A TTL~50ns Ststb !1 Page RAM Interface Interfacing the 8080 CPU to Memory and I/O DevicesROM Interface Ill General Theory InterfaceIsolated I/O Memory Mapped I/OMemr to AddressingInterface Example 15 Format 13 Format8080 Instruction SET Instruction and Data FormatsByte Two Byte OneByte Three I D7 Addressing ModesSymbols Meaning Symbols and AbbreviationsDescription Format AllData Transfer Group Content of register r2 is moved to register r1MOV r1, r2 Move Register Reg. indirect0 I R 0 I R pArithmetic Group 0 I1 I 0 I 0 o0 I D I D R 0 ILogical Group I IOCR M Decrement memory Cycles States Addressing reg. indirect Flags Z,S,P ,CY,ACI 1 I 1 o I 1 I 1 I I 0 I 1 I 1 I~11~ 1 1 10 I 0 1 I 0 I 1 I0 I 0 I Cycles States Flags none000 Branch GroupSP ~ SP + I c c I c I 0 I 0 ICcondition addr I 1 o Stack, I/O, and Machine Control GroupPush rp 1 I R~ SP + Exchange stack top with Hand L~ data Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky BipolarGeneral Functional DescriptionOscillator Clock GeneratorStstb Status Strobe Power-On Reset and Ready Flip-FlopsCrystal Requirements Characteristics8pF InputExample Characteristics For tCY = 488.28 nsT42 T01 T02 T03 Toss TORS tORH tOR FMAXDbin PIN Configuration Block DiagramBlock GeneralInta None Control SignalsTE~r Characteristics TA = Oc to 70C Vee = 5V ±5%Waveforms Hlda to Read Status OutputsStstb GoUTVTH VCC=5VGND ---. r ·-c?oo .H Intel Silicon Gate MOS 8080 a8080A Functional PIN Definition VeeVss Absolute Maximum RATINGS· CharacteristicsCapacitance IOl = 1.9mA on all outputs~I~~~ =..... -r-DATAINTiming Waveforms ~~1 t CYTypical ~ Output Delay VS. a Capacitance CharacteristicsTypical Instructions Instruction SETSummary of Processor Instructions Silicon Gate MOS 8080.AInfel Silicon Gate MOS 8080A-1 Unit Symbol Parameter TypMax ~-t Fft~l~tOF.I TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 Cout +10J1A VAOOR/OATA = VSS + O.45VUnit Test Condition Symbol Parameter MinMin. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Register to regist~r, memory refer Immediate mode or I/O instructionsEnce, arithmetic or logical, rotate Interrupt instructionsLlf17 Summary of Processor InstructionsM8080A Functional PIN Definition Silicon Gate MOS M8080AOperation Absolute Maximum RatingsIOL = 1.9mA on all outputs Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A Voo Operating CharacteristicsPIN Connections 1N= Vee Switching Characteristics~10% = V ceCs=o.~ \ \Symbol Test Operating Characteristics for Programming OperationCharacteristics for Programming Operation SYMBOLTESTMIN. TYP. MAX. Unit ConditionsCS = OV Switching Characteristics for Programming OperationProgramming Operation of the 8702A Program OperationII. Programming of the 8702A Using Intel Microcomputers Operation of the 8702A in Program ModeIII a Erasing Procedure Programming Instructions for the 8702APage PIN Names PIN Configurations Block DiagramIII CommentIBB VOH1Test Conditions Symbol Parameter Typ. Max. Unit ConditionsWaveforms Max UnitProgramming Current RnA Program Pulse Amplitude Parameter MinTpF Program Pulse Fall Time +-------1 Read/Program/Read TransitionsCS/WE = +12V PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 rSilicon Gate MOS MAX Unit CommentCS=O.O Outa200ns 500ns 300 ns ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\100 ns 7001 JJ.s Cs .. o.~ ~r Typical CharacteristicsSilicon Gate MOS Ilpc IlclIlkc ILOCIN Conditions of Test for CharacteristicsCoUT ~ ~ ~ Marking Mask Option SpecificationsPppp Customer Number OateTitle Card ~ r ------ + -- t --- . L . ------ rJBlank 79-80Intel Silicon Gate MOS ROM 8316A PIN Configuration Block DiagramCAPACITANCE2 TA = 25C, f = 1 MHz 400Conditions of Test for Waveforms OU~TVALIDILICO.N Gate MOS ROM 8316A Typical D.C. CharacteristicsNumber Oate CustomerSTO Mask Option Speci FicationsCOM~ANY Name Title CardRAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram= OC ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=10H = -150 p.A +----+00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block DiagramIII Symbol Parameter Min. Typ.rICC1 ICC2550 200 Write 1~-tAW--.I-----IInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level VoltPage Silicon Gate MOS 5V to +7V Power Dissipation WattComment TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified+--~~~TL~~~EEt~~~P-.± 85o-·-···TCapacitance T a = 25C, f = 1MHz Conditions of Test~~~b~.J Typical A.C. CharacteristicsSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 300 450230 Access Time VS Ambient Temperature VIN Limits VS. TemperatureAccess Time VS LOAD·CAPACITANCE Output Source Current VSPIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic MemoryIOOAV2 Silicon Gate MOS 81078·4IMP~ri~~CE II.~4000 Read CycleRef = Write CycleTypical Characteristics Numbers in parentheses are for minimum cycle timing in ns Symbol Parameter Min MaxRWc 590 CD Standby Power Power DissipationRefresh System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM VIH VOL VOH ICC2VOR IcccrTiming Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic SymbolVoo- --- ---T Conditions of TestAll driver outputs are in the state indicated Power Supply Current Drain and Power DissipationTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic DiagramOS2 Functional DescriptionII. Gated Buffer 3·STATE Basic Schematic SymbolsAre 3-state Gated BufferIV. Interrupting Input Port III. Bi-Directional Bus DriverInterrupt Instruction Port BI-DIRECTIONAL BUS DriverVII Status Latch VI. Output Port With Hand-Shaking8080 4 OvJ \.. -4~OUT Viii SystemVee SystemIX System 1G~D L-~ DalN-t?!NrJAbsolute Maximum Ratings· Characteristics052 ~ Typical CharacteristicsTpw OUT12 pF Switching CharacteristicsTA = OC to + 75C Vee = +5V ± 5% ~~~lEI~S 1-- +SV Programmable Peripheral InterfaceData Bus Buffer GeneralRead/Write and Control Logic Basic Functional DescriptionPIN Configuration ResetGroup a and Group B Controls Ports A, B, and CSingle Bit Set/Reset Feature Mode SelectionDetailed Operational Description PA 7 ·pAoInterrupt Control Functions Operating Modes Mode 0 Basic Input/OutputMode 0 Timing Mode 0 Configurations Mode 0 Port Definition Chart119 · / ,4 Operating Modes Mode 1 Strobed Input/OutputIBF Input Buffer Full F/F Input Control Signal DefinitionIntr Interrupt Request Inte aIntea Output Control Signal DefinitionBi-Directional Bus I/O Control Signal Definition Combinations of ModeOperating Modes Output OperationsMode 2 Bi-directional Timing Mode 2 Control WordMode 2 and Mode 0 Output Mode 2 CombinationsMode Definition Summary Table Special Mode Combination ConsiderationsSource Current Capability on Port B and Port C Reading Port C StatusPrinter Interface ApplicationsKeyboard and Display Interface Keyboard and Terminal Address Interface~.LEFT/RIGHT PCOSilicon Gate MOS Vil Input Low Voltage Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVInput High Voltage Val Output Low Voltage IOl = 1.6mA Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface General Reset ResetReadlWrite Control logic ClK ClockDSR Data Set Ready Modem ControlTxE Transmitter Empty DTR Data Termin·al ReadyReceiver Control Receiver BufferRxRDY Receiver Ready RxC Receiver ClockCommand Instruction Mode InstructionDetailed Operation Description ProgrammingAsynchronous Mode Transmission Mode Instruction DefinitionAsynchronous Mode Receive Data C~~RACTERSynchronous Mode Receive Synchronous Mode TransmissionMode Instruction Format, Synchronous Mode Synchronous Mode, Transmission FormatCommand Instruction Format Command Instruction DefinitionStatus Read Definition Status Read FormatAsynchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudSynchronous Interface to Terminal or Peripheral Device Synchronous Interface to Telephone LinesIOL CapacitanceIcc Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol ParameterSRX ~4IlI RxD~AST BIT ,----1 RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder System Enable GateDecoder Port Decoder Using a very similar circuit to the I/O port decoder, an arChip Select Decoder 24K Memory Interface\lJ Logic Element ExampleJJ,.--+-I----.....1 IllTypical Characteristics Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Symbol VOL VOH 8205Address or Enable to Output Delay VS. Load Capacitance Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Ambient Temperature Test Waveforms~ ~ PIN Configuration~ R Interrupt Method Interrupts in Microcomputer SystemsPolled Method Current Status Register Priority EncoderINTE, elK Control SignalsElR, ETlG, ENGl AO, A1, A2Basic Operation Level ControllerLevel Controller I ICascading Symbol Parameter Limits Unit Conditions Min Typ.£1 Operating CharacteristicsLos Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n csControl Gating OlEN, CS Bi-Directional DriverLarge microcomputer systems it is often necessary to pro Applications of 8216/8226Memory and 1/0 Interface to a Bi-directional Bus Input Load Current OlEN, CS VF =0.45 IcC Power Supply Current 120Input Load Current All Other Inputs VF =0.45 Input Leakage Current OlEN, CS VR =5.25VOUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval TimerPreliminary Functional Description Block DiagramSystem Interface System InterfaceProgrammable DMA Controller System Application System InterfaceDack 2 CS-------It LJJ ROMs RAMs CPU GroupPeripheral Coming Soon IntelIt-j ~~~1735~ ·34o~ \.--.J.. ~~~lLead Plastic Dual IN-LINE Package P Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SETMicrocomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel CorporationInter
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8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.
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