Contents
Page
Programmable Communication Interface
Clock Generator for 8080A
System Controller for 8080A
Programmable Peripheral Interface
Contents
Peri pherals
127
Chapter Packaging Information
Page
Microcomputer Design Aids
Advantages of Designing With Microcomputers
Conventional System Programmed Logic
Iii
Applications Example
1IIII~Iff1
Application
Peripheral Devices Encountered
Architecture of a CPU
Typical Computer System
Accumulator
Program Counter Jumps, Subroutines and the Stack
Instruction Register and Decoder
Arithmetic/Logic Unit ALU
Control Circuitry
Address Registers
Computer Operations
Memory Write
Instruction Fetch
Memory Read
Wait memory synchronization
Page
Page
INTE~
8080 Photomicrograph With Pin Designations
Architecture of the 8080 CPU
Registers
Data Bus Buffer
Arithmetic and Logic Unit ALU
Instruction Register and Control
Processor Cycle
Machine Cycle Identification
State Transition Sequence
Halt
Status Bit Definitions
Status Word Chart
Status Information Definition
CPU State Transition Diagram
?~~
Rr\
ONE ,----- ~
State Associated Activities
~2. State Definitions
RLrL- rL rL rL-rL- rLrL
Interrupt Sequences
¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL
Halt Sequences
Hold Sequences
START-UP of the 8080 CPU
11. Halt Timing
~~~~t==p
001
STATUS6
Xram
~A~~~ll
~iA~~~11
~iA~~ll,12
~iA~~~11
Value
111 000 001 010 011 100 101
Typical Computer System Block Diagram
Basic System Operation
Clock Generator and High Level Driver
CPU Module Design
8080 CPU
Clock Generator Design
~50ns
ClK 0.......-..-.-----.. tf1A TTL
High Level Driver Design
Ststb !1
Page
ROM Interface
Interfacing the 8080 CPU to Memory and I/O Devices
RAM Interface
Ill
Isolated I/O
Interface
General Theory
Memory Mapped I/O
Interface Example
Addressing
Memr to
13 Format
15 Format
Instruction and Data Formats
8080 Instruction SET
Byte Three I D7
Byte One
Byte Two
Addressing Modes
Description Format
Symbols and Abbreviations
Symbols Meaning
All
MOV r1, r2 Move Register
Content of register r2 is moved to register r1
Data Transfer Group
Reg. indirect
0 I R p
0 I R
1 I
0 I
Arithmetic Group
0 I 0 o
R 0 I
0 I D I D
OCR M Decrement memory
I I
Logical Group
Cycles States Addressing reg. indirect Flags Z,S,P ,CY,AC
~11~
I 0 I 1 I 1 I
I 1 I 1 o I 1 I 1 I
1 1 1
0 I 0 I
0 I 1 I
0 I 0 1 I
Cycles States Flags none
Branch Group
000
Ccondition addr
I c c I c I 0 I 0 I
SP ~ SP +
Push rp
Stack, I/O, and Machine Control Group
I 1 o
1 I R
~ data
Exchange stack top with Hand L
~ SP +
Cycles States Flags None
Instruction SET
Programmable Peripheral Interface
8224 8080A-1 8228 8080A-2 8080A M8080-A
Page
Schottky Bipolar
PIN Names
Oscillator
Functional Description
General
Clock Generator
Power-On Reset and Ready Flip-Flops
Ststb Status Strobe
Characteristics
Crystal Requirements
Input
8pF
T42 T01 T02 T03 Toss
Characteristics For tCY = 488.28 ns
Example
TORS tORH tOR FMAX
PIN Configuration Block Diagram
Dbin
General
Block
Signals
Inta None Control
Waveforms
Characteristics TA = Oc to 70C Vee = 5V ±5%
TE~r
Hlda to Read Status Outputs
VTH
GoUT
Ststb
VCC=5V
·-c
GND ---. r
Intel Silicon Gate MOS 8080 a
?oo .H
Vss
Vee
8080A Functional PIN Definition
Capacitance
Characteristics
Absolute Maximum RATINGS·
IOl = 1.9mA on all outputs
Timing Waveforms
=..... -r-DATAIN
~I~~~
~~1 t CY
Characteristics
Typical ~ Output Delay VS. a Capacitance
Instruction SET
Typical Instructions
Silicon Gate MOS 8080.A
Summary of Processor Instructions
Infel Silicon Gate MOS 8080A-1
Max
Symbol Parameter Typ
Unit
~tOF.I
Fft~l
~-t
TYPICAL!J. Output Delay VS. ~ Capacitance
Infel Silicon Gate MOS 8080 A-2
J1A
+10
Cout
VAOOR/OATA = VSS + O.45V
Symbol Parameter Min
Unit Test Condition
Typical ~ Output Delay VS. ~ Capacitance
Min. Max. Unit Test Condition
Page
Intel . Silicon Gate MOS M8080A
Ence, arithmetic or logical, rotate
Immediate mode or I/O instructions
Register to regist~r, memory refer
Interrupt instructions
Summary of Processor Instructions
Llf17
Silicon Gate MOS M8080A
M8080A Functional PIN Definition
IOL = 1.9mA on all outputs
Absolute Maximum Ratings
Operation
Symbol Parameter Min. Max Unit Test Condition
Silicon Gate MOS M8080A
~I~
Page
ROMs 8702A 8704 8708 8316A
Page
Silicon Gate MOS 8702A
PIN Connections
Operating Characteristics
Voo
~10%
Switching Characteristics
1N= Vee
= V ce
\ \
Cs=o.~
Characteristics for Programming Operation
Operating Characteristics for Programming Operation
Symbol Test
SYMBOLTESTMIN. TYP. MAX. Unit Conditions
Programming Operation of the 8702A
Switching Characteristics for Programming Operation
CS = OV
Program Operation
III a Erasing Procedure
Operation of the 8702A in Program Mode
II. Programming of the 8702A Using Intel Microcomputers
Programming Instructions for the 8702A
Page
PIN Configurations Block Diagram
PIN Names
IBB
Comment
III
VOH1
Waveforms
Symbol Parameter Typ. Max. Unit Conditions
Test Conditions
Max Unit
TpF Program Pulse Fall Time
Parameter Min
Programming Current RnA Program Pulse Amplitude
CS/WE = +12V
Read/Program/Read Transitions
+-------1
150 r
PEEEf!1EJEZPlEzz$m=2!·m·· Icc
Silicon Gate MOS
CS=O.O
Comment
MAX Unit
Outa
100 ns 7001 JJ.s
~~~H --4!~--~N-~-TA-AL-~-DU-T--~\
200ns 500ns 300 ns
Typical Characteristics
Cs .. o.~ ~r
Silicon Gate MOS
Ilkc
Ilcl
Ilpc
ILO
CoUT
Conditions of Test for Characteristics
CIN
~ ~ ~
Pppp
Mask Option Specifications
Marking
Customer Number Oate
Blank
~ r ------ + -- t --- . L . ------ rJ
Title Card
79-80
PIN Configuration Block Diagram
Intel Silicon Gate MOS ROM 8316A
Conditions of Test for
400
CAPACITANCE2 TA = 25C, f = 1 MHz
OU~TVALID
Waveforms
Typical D.C. Characteristics
ILICO.N Gate MOS ROM 8316A
STO
Customer
Number Oate
Mask Option Speci Fications
Title Card
COM~ANY Name
RAMs
Page
PIN Configuration Logic Symbol Block Diagram
Silicon Gate MOS
10H = -150 p.A
~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~=
= OC
+----+
Conditions of Test
00 ~
Page
PIN Configuration Logic Symbol Block Diagram
Silicon Gate MOS
ICC1
Symbol Parameter Min. Typ.r
III
ICC2
Input Pulse Rise and Fall Times 20nsec
Write 1~-tAW--.I-----I
550 200
Timing Measurement Reference Level Volt
Page
Silicon Gate MOS
Comment
Power Dissipation Watt
5V to +7V
TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified
Capacitance T a = 25C, f = 1MHz
85o-·-···T
+--~~~TL~~~EEt~~~P-.±
Conditions of Test
Typical A.C. Characteristics
~~~b~.J
Silicon Gate MOS 8102A-4
TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified
230
450
300
Access Time VS LOAD·CAPACITANCE
VIN Limits VS. Temperature
Access Time VS Ambient Temperature
Output Source Current VS
Fully Decoded Random Access BIT Dynamic Memory
PIN Configuration Logic Symbol Block Diagram
Silicon Gate MOS 81078·4
IOOAV2
II.~
IMP~ri~~CE
Ref =
Read Cycle
4000
Write Cycle
Typical Characteristics
RWc 590 CD
Symbol Parameter Min Max
Numbers in parentheses are for minimum cycle timing in ns
Refresh
Power Dissipation
Standby Power
System Interfaces and Filtering
Typical System
BIT 256 x 4 Static Cmos RAM
VOR
ICC2
VIH VOL VOH
Icccr
Input Pulse Rise and Fall Times 20nsec
Timing Measurement Reference Level Volt
~I----- t CW2 ------ . t
PIN Configuration Logic Symbol
Schottky Bipolar
Conditions of Test
Voo- --- ---T
Power Supply Current Drain and Power Dissipation
All driver outputs are in the state indicated
Typical System
Dynamic Memory Refresh Controller
Page
8212 8255 8251
Page
PIN Configuration Logic Diagram
EIGHT-BIT INPUT/OUTPUT Port
Functional Description
OS2
Are 3-state
Basic Schematic Symbols
II. Gated Buffer 3·STATE
Gated Buffer
Interrupt Instruction Port
III. Bi-Directional Bus Driver
IV. Interrupting Input Port
BI-DIRECTIONAL BUS Driver
8080 4
VI. Output Port With Hand-Shaking
VII Status Latch
OvJ \.. -4~
Vee
Viii System
OUT
System
IX System
DalN-t?!NrJ
1G~D L-~
Characteristics
Absolute Maximum Ratings·
Typical Characteristics
052 ~
OUT
Tpw
TA = OC to + 75C Vee = +5V ± 5%
Switching Characteristics
12 pF
Programmable Peripheral Interface
~~~lEI~S 1-- +SV
Read/Write and Control Logic
General
Data Bus Buffer
Basic Functional Description
Group a and Group B Controls
Reset
PIN Configuration
Ports A, B, and C
Detailed Operational Description
Mode Selection
Single Bit Set/Reset Feature
PA 7 ·pAo
Mode 0 Timing
Operating Modes Mode 0 Basic Input/Output
Interrupt Control Functions
Mode 0 Port Definition Chart
Mode 0 Configurations
119
Operating Modes Mode 1 Strobed Input/Output
· / ,4
Intr Interrupt Request
Input Control Signal Definition
IBF Input Buffer Full F/F
Inte a
Output Control Signal Definition
Intea
Operating Modes
Combinations of Mode
Bi-Directional Bus I/O Control Signal Definition
Output Operations
Mode 2 Control Word
Mode 2 Bi-directional Timing
Mode 2 Combinations
Mode 2 and Mode 0 Output
Source Current Capability on Port B and Port C
Special Mode Combination Considerations
Mode Definition Summary Table
Reading Port C Status
Keyboard and Display Interface
Applications
Printer Interface
Keyboard and Terminal Address Interface
PCO
~.LEFT/RIGHT
Silicon Gate MOS
Input High Voltage Val Output Low Voltage IOl = 1.6mA
Characteristics TA = oc to 70C Vee = +5V ±5% vss = OV
Vil Input Low Voltage
Time From STB = 0 To IBF
Mode 0 Basic Input
Mode 1 Strobed Input
Mode 2 Bi-directional
Page
Programmable Communication Interface
ReadlWrite Control logic
Reset Reset
General
ClK Clock
TxE Transmitter Empty
Modem Control
DSR Data Set Ready
DTR Data Termin·al Ready
RxRDY Receiver Ready
Receiver Buffer
Receiver Control
RxC Receiver Clock
Detailed Operation Description
Mode Instruction
Command Instruction
Programming
Asynchronous Mode Receive
Mode Instruction Definition
Asynchronous Mode Transmission
Data C~~RACTER
Mode Instruction Format, Synchronous Mode
Synchronous Mode Transmission
Synchronous Mode Receive
Synchronous Mode, Transmission Format
Status Read Definition
Command Instruction Definition
Command Instruction Format
Status Read Format
Synchronous Interface to Terminal or Peripheral Device
Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud
Asynchronous Interface to Telephone Lines
Synchronous Interface to Telephone Lines
Icc
Capacitance
IOL
TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter
Typ
~AST BIT ,----1
RxD
SRX ~4IlI
RXD~
Peripherals
Page
High Speed 1 OUT of 8 Binary Decoder
Decoder
Enable Gate
System
Chip Select Decoder
Using a very similar circuit to the I/O port decoder, an ar
Port Decoder
24K Memory Interface
JJ,.--+-I----.....1
Logic Element Example
\lJ
Ill
Symbol VOL VOH
Characteristics TA = OOC to +75C, Vee = 5.0V ±5%
Typical Characteristics
8205
Address or Enable to Output Delay VS. Ambient Temperature
Switching Characteristics Conditions of Test Test Load
Address or Enable to Output Delay VS. Load Capacitance
Test Waveforms
~ R
PIN Configuration
~ ~
Polled Method
Interrupts in Microcomputer Systems
Interrupt Method
Priority Encoder
Current Status Register
ElR, ETlG, ENGl
Control Signals
INTE, elK
AO, A1, A2
Level Controller
Basic Operation
I I
Level Controller
Cascading
Los
Operating Characteristics
Symbol Parameter Limits Unit Conditions Min Typ.£1
Absolute Maximum Ratings
Characteristics and Waveforms TA = oc to +70C, vcc = +5V ±5%
Schottky Bipolar
+-......---- n cs
8216 8226
Bi-Directional Driver
Control Gating OlEN, CS
Memory and 1/0 Interface to a Bi-directional Bus
Applications of 8216/8226
Large microcomputer systems it is often necessary to pro
Input Load Current All Other Inputs VF =0.45
IcC Power Supply Current 120
Input Load Current OlEN, CS VF =0.45
Input Leakage Current OlEN, CS VR =5.25V
Waveforms
OUT
Page
8253 8257 8259
Page
Programmable Interval Timer
It uses nMOS technology ~Jmodesof operation are
System Interface
Block Diagram
Preliminary Functional Description
System Interface
Programmable DMA Controller
Dack 2
System Interface
System Application
CS-------It
LJJ
Peripheral Coming Soon
CPU Group
ROMs RAMs
Intel
735~
~~~1
It-j
Lead Plastic Dual IN-LINE Package P
\.--.J.. ~~~l
·34o~
Lead CerDIP Dual IN-LINE Package D
Sales and Marketing Offices
Distributors
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Instruction SET
Instruction SET
Summary of Processor Instructions By Alphabetical Order
Microcomputer System Users Registration Card
Intel Corporation
Microcomputer Systems Bowers Avenue Santa Clara, CA
Inter
