Intel 8080 manual Absolute Maximum Ratings, IOL = 1.9mA on all outputs, Operation

Page 95

SILICON GATE MOS M8080A

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias

-55°C to +125°C

Storage T emperatu re

_65°C to + 150°C

All Input or Output Voltages

 

With Respect to VBB

-0.3V to +20V

Vcc, Voo and Vss With Respect to VBB

-0.3V to +20V

Power Dissipation

. . . . . . .. 1.7W

*COMMENT: Stresses above those listed under "Absolute Maxi- mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or any other conditions above those indicated in the operational sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS

TA = -55°C to +125°C, VOD = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted.

Symbol

Parameter

Min.

Typ.

Max.

VILC

Clock Input Low Voltage

Vss-l

 

Vss+0.8

VIHC

Clock Input High Voltage

8.5

 

Voo+1

VIL

Input Low Voltage

Vss-l

 

Vss +0.8

VIH

Input High Voltage

3.0

 

Vcc+1

VOL

Output Low Voltage

 

 

0.45

VO H

Output High Voltage

3.7

 

 

IOD(AV)

Avg. Power Supply Current (Voo )

 

50

80

ICC (AV)

Avg. Power Supply Current (Vec)

 

60

100

IBB(AV)

Avg. Power Supply Current (VBB )

 

.01

1

IlL

Input Leakage

 

 

±10

ICL

Clock Leakage

 

 

±10

IDL [2]

Data Bus Leakage in Input Mode

 

 

-100

 

 

 

 

-2.0

IFL

Address and Data Bus Leakage

 

 

+10

During HOLD

 

 

-100

 

 

 

Unit

V

V

V

V

V

V rnA mA mA J1A J1A

J1A rnA

J1A

Test Condition

}IOL = 1.9mA on all outputs,

IOH = 150J-lA.

} Operation

TCy = .48 J.1.sec

Vss ~ VIN ~ Vcc

Vss ~ VCLOCK ~ VDD

VSS ~VIN ~VSS +O.~V

VSS +0.8V ~VIN ~VCC

VADDR/DATA = VCC VADDR/DATA = Vss + O.45V

CAPACITANCE

TA = 25°C

Vec = VOD = Vss = OV, VBB =-5V

 

Symbol

Parameter

Typ.

Max.

Unit

C¢

Clock Capacitance

17

25

pf

CIN

Input Capacitance

6

10

pf

CO UT

Output Capacitance

10

20

pf

NOTES:

 

 

 

 

1.The RESET signal must be active for a minimum of 3 clock cycles.

2.When DBIN is high and VIN > VIH an internal active pull up will be switched onto the Oata Bus.

3.~I supply / ~TA = -0.45%/C.

Test Condition

fc = 1 MHz

Unmeasured Pins

Returned to Vss

I-

2

~

a:

:::>

u

>

...J

8:

:::>

en

TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZEO.l3]

1 . 5, ..... ------ r ----------- ,

1.0J---------:::::l~I------______I

0.5t ------ J ------- ______ I

-55+50+125

AMBIENT TEMPERATURE rc)

DATA BUS CHARACTERISTIC

DURING DBIN

MAX

°0"----------------------

30--

Vee

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Contents Page Programmable Peripheral Interface Clock Generator for 8080ASystem Controller for 8080A Programmable Communication InterfaceContents Chapter Packaging Information 127Peri pherals Page Conventional System Programmed Logic Advantages of Designing With MicrocomputersMicrocomputer Design Aids 1IIII~Iff1 Applications ExampleIii Peripheral Devices Encountered ApplicationAccumulator Typical Computer SystemArchitecture of a CPU Instruction Register and Decoder Program Counter Jumps, Subroutines and the StackComputer Operations Control CircuitryAddress Registers Arithmetic/Logic Unit ALUWait memory synchronization Instruction FetchMemory Read Memory WritePage Page 8080 Photomicrograph With Pin Designations INTE~Registers Architecture of the 8080 CPUProcessor Cycle Arithmetic and Logic Unit ALUInstruction Register and Control Data Bus BufferMachine Cycle Identification Halt State Transition SequenceStatus Information Definition Status Word ChartStatus Bit Definitions ?~~ CPU State Transition DiagramRr\ ONE ,----- ~ ~2. State Definitions State Associated ActivitiesInterrupt Sequences RLrL- rL rL rL-rL- rLrL¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL START-UP of the 8080 CPU Hold SequencesHalt Sequences 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~iA~~~11 ~iA~~~11~iA~~ll,12 ~A~~~ll111 000 001 010 011 100 101 ValueBasic System Operation Typical Computer System Block DiagramClock Generator Design CPU Module Design8080 CPU Clock Generator and High Level DriverHigh Level Driver Design ClK 0.......-..-.-----.. tf1A TTL~50ns Ststb !1 Page RAM Interface Interfacing the 8080 CPU to Memory and I/O DevicesROM Interface Ill Memory Mapped I/O InterfaceGeneral Theory Isolated I/OMemr to AddressingInterface Example 15 Format 13 Format8080 Instruction SET Instruction and Data FormatsAddressing Modes Byte OneByte Two Byte Three I D7All Symbols and AbbreviationsSymbols Meaning Description FormatReg. indirect Content of register r2 is moved to register r1Data Transfer Group MOV r1, r2 Move Register0 I R 0 I R p0 I 0 o 0 IArithmetic Group 1 I0 I D I D R 0 ICycles States Addressing reg. indirect Flags Z,S,P ,CY,AC I ILogical Group OCR M Decrement memory1 1 1 I 0 I 1 I 1 II 1 I 1 o I 1 I 1 I ~11~Cycles States Flags none 0 I 1 I0 I 0 1 I 0 I 0 I000 Branch GroupSP ~ SP + I c c I c I 0 I 0 ICcondition addr 1 I R Stack, I/O, and Machine Control GroupI 1 o Push rpCycles States Flags None Exchange stack top with Hand L~ SP + ~ dataInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page PIN Names Schottky BipolarClock Generator Functional DescriptionGeneral OscillatorStstb Status Strobe Power-On Reset and Ready Flip-FlopsCrystal Requirements Characteristics8pF InputTORS tORH tOR FMAX Characteristics For tCY = 488.28 nsExample T42 T01 T02 T03 TossDbin PIN Configuration Block DiagramBlock GeneralInta None Control SignalsHlda to Read Status Outputs Characteristics TA = Oc to 70C Vee = 5V ±5%TE~r WaveformsVCC=5V GoUTStstb VTHGND ---. r ·-c?oo .H Intel Silicon Gate MOS 8080 a8080A Functional PIN Definition VeeVss IOl = 1.9mA on all outputs CharacteristicsAbsolute Maximum RATINGS· Capacitance~~1 t CY =..... -r-DATAIN~I~~~ Timing WaveformsTypical ~ Output Delay VS. a Capacitance CharacteristicsTypical Instructions Instruction SETSummary of Processor Instructions Silicon Gate MOS 8080.AInfel Silicon Gate MOS 8080A-1 Unit Symbol Parameter TypMax ~-t Fft~l~tOF.I TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 VAOOR/OATA = VSS + O.45V +10Cout J1AUnit Test Condition Symbol Parameter MinMin. Max. Unit Test Condition Typical ~ Output Delay VS. ~ CapacitancePage Intel . Silicon Gate MOS M8080A Interrupt instructions Immediate mode or I/O instructionsRegister to regist~r, memory refer Ence, arithmetic or logical, rotateLlf17 Summary of Processor InstructionsM8080A Functional PIN Definition Silicon Gate MOS M8080AOperation Absolute Maximum RatingsIOL = 1.9mA on all outputs Symbol Parameter Min. Max Unit Test Condition ~I~ Silicon Gate MOS M8080APage ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A Voo Operating CharacteristicsPIN Connections = V ce Switching Characteristics1N= Vee ~10%Cs=o.~ \ \SYMBOLTESTMIN. TYP. MAX. Unit Conditions Operating Characteristics for Programming OperationSymbol Test Characteristics for Programming OperationProgram Operation Switching Characteristics for Programming OperationCS = OV Programming Operation of the 8702AProgramming Instructions for the 8702A Operation of the 8702A in Program ModeII. Programming of the 8702A Using Intel Microcomputers III a Erasing ProcedurePage PIN Names PIN Configurations Block DiagramVOH1 CommentIII IBBMax Unit Symbol Parameter Typ. Max. Unit ConditionsTest Conditions WaveformsProgramming Current RnA Program Pulse Amplitude Parameter MinTpF Program Pulse Fall Time +-------1 Read/Program/Read TransitionsCS/WE = +12V PEEEf!1EJEZPlEzz$m=2!·m·· Icc 150 rSilicon Gate MOS Outa CommentMAX Unit CS=O.O200ns 500ns 300 ns ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\100 ns 7001 JJ.s Cs .. o.~ ~r Typical CharacteristicsSilicon Gate MOS ILO IlclIlpc IlkcCIN Conditions of Test for CharacteristicsCoUT ~ ~ ~ Customer Number Oate Mask Option SpecificationsMarking Pppp79-80 ~ r ------ + -- t --- . L . ------ rJTitle Card BlankIntel Silicon Gate MOS ROM 8316A PIN Configuration Block DiagramCAPACITANCE2 TA = 25C, f = 1 MHz 400Conditions of Test for Waveforms OU~TVALIDILICO.N Gate MOS ROM 8316A Typical D.C. CharacteristicsMask Option Speci Fications CustomerNumber Oate STOCOM~ANY Name Title CardRAMs Page Silicon Gate MOS PIN Configuration Logic Symbol Block Diagram+----+ ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~== OC 10H = -150 p.A00 ~ Conditions of TestPage Silicon Gate MOS PIN Configuration Logic Symbol Block DiagramICC2 Symbol Parameter Min. Typ.rIII ICC1Timing Measurement Reference Level Volt Write 1~-tAW--.I-----I550 200 Input Pulse Rise and Fall Times 20nsecPage Silicon Gate MOS TA = OOC to +70C, Vee = 5V ±5% unless otherwise specified Power Dissipation Watt5V to +7V CommentConditions of Test 85o-·-···T+--~~~TL~~~EEt~~~P-.± Capacitance T a = 25C, f = 1MHz~~~b~.J Typical A.C. CharacteristicsSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 300 450230 Output Source Current VS VIN Limits VS. TemperatureAccess Time VS Ambient Temperature Access Time VS LOAD·CAPACITANCEPIN Configuration Logic Symbol Block Diagram Fully Decoded Random Access BIT Dynamic MemoryIOOAV2 Silicon Gate MOS 81078·4IMP~ri~~CE II.~Write Cycle Read Cycle4000 Ref =Typical Characteristics Numbers in parentheses are for minimum cycle timing in ns Symbol Parameter Min MaxRWc 590 CD System Interfaces and Filtering Power DissipationStandby Power RefreshTypical System BIT 256 x 4 Static Cmos RAM Icccr ICC2VIH VOL VOH VORTiming Measurement Reference Level Volt Input Pulse Rise and Fall Times 20nsec~I----- t CW2 ------ . t Schottky Bipolar PIN Configuration Logic SymbolVoo- --- ---T Conditions of TestAll driver outputs are in the state indicated Power Supply Current Drain and Power DissipationTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page EIGHT-BIT INPUT/OUTPUT Port PIN Configuration Logic DiagramOS2 Functional DescriptionGated Buffer Basic Schematic SymbolsII. Gated Buffer 3·STATE Are 3-stateBI-DIRECTIONAL BUS Driver III. Bi-Directional Bus DriverIV. Interrupting Input Port Interrupt Instruction PortOvJ \.. -4~ VI. Output Port With Hand-ShakingVII Status Latch 8080 4System Viii SystemOUT VeeIX System 1G~D L-~ DalN-t?!NrJAbsolute Maximum Ratings· Characteristics052 ~ Typical CharacteristicsTpw OUT12 pF Switching CharacteristicsTA = OC to + 75C Vee = +5V ± 5% ~~~lEI~S 1-- +SV Programmable Peripheral InterfaceBasic Functional Description GeneralData Bus Buffer Read/Write and Control LogicPorts A, B, and C ResetPIN Configuration Group a and Group B ControlsPA 7 ·pAo Mode SelectionSingle Bit Set/Reset Feature Detailed Operational DescriptionInterrupt Control Functions Operating Modes Mode 0 Basic Input/OutputMode 0 Timing Mode 0 Configurations Mode 0 Port Definition Chart119 · / ,4 Operating Modes Mode 1 Strobed Input/OutputInte a Input Control Signal DefinitionIBF Input Buffer Full F/F Intr Interrupt RequestIntea Output Control Signal DefinitionOutput Operations Combinations of ModeBi-Directional Bus I/O Control Signal Definition Operating ModesMode 2 Bi-directional Timing Mode 2 Control WordMode 2 and Mode 0 Output Mode 2 CombinationsReading Port C Status Special Mode Combination ConsiderationsMode Definition Summary Table Source Current Capability on Port B and Port CKeyboard and Terminal Address Interface ApplicationsPrinter Interface Keyboard and Display Interface~.LEFT/RIGHT PCOSilicon Gate MOS Time From STB = 0 To IBF Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVVil Input Low Voltage Input High Voltage Val Output Low Voltage IOl = 1.6mAMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface ClK Clock Reset ResetGeneral ReadlWrite Control logicDTR Data Termin·al Ready Modem ControlDSR Data Set Ready TxE Transmitter EmptyRxC Receiver Clock Receiver BufferReceiver Control RxRDY Receiver ReadyProgramming Mode InstructionCommand Instruction Detailed Operation DescriptionData C~~RACTER Mode Instruction DefinitionAsynchronous Mode Transmission Asynchronous Mode ReceiveSynchronous Mode, Transmission Format Synchronous Mode TransmissionSynchronous Mode Receive Mode Instruction Format, Synchronous ModeStatus Read Format Command Instruction DefinitionCommand Instruction Format Status Read DefinitionSynchronous Interface to Telephone Lines Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudAsynchronous Interface to Telephone Lines Synchronous Interface to Terminal or Peripheral DeviceIOL CapacitanceIcc Typ TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol ParameterRXD~ RxDSRX ~4IlI ~AST BIT ,----1Peripherals Page High Speed 1 OUT of 8 Binary Decoder System Enable GateDecoder 24K Memory Interface Using a very similar circuit to the I/O port decoder, an arPort Decoder Chip Select DecoderIll Logic Element Example\lJ JJ,.--+-I----.....18205 Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Typical Characteristics Symbol VOL VOHTest Waveforms Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Load Capacitance Address or Enable to Output Delay VS. Ambient Temperature~ ~ PIN Configuration~ R Interrupt Method Interrupts in Microcomputer SystemsPolled Method Current Status Register Priority EncoderAO, A1, A2 Control SignalsINTE, elK ElR, ETlG, ENGlBasic Operation Level ControllerLevel Controller I ICascading Absolute Maximum Ratings Operating CharacteristicsSymbol Parameter Limits Unit Conditions Min Typ.£1 LosCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar 8216 8226 +-......---- n csControl Gating OlEN, CS Bi-Directional DriverLarge microcomputer systems it is often necessary to pro Applications of 8216/8226Memory and 1/0 Interface to a Bi-directional Bus Input Leakage Current OlEN, CS VR =5.25V IcC Power Supply Current 120Input Load Current OlEN, CS VF =0.45 Input Load Current All Other Inputs VF =0.45OUT WaveformsPage 8253 8257 8259 Page It uses nMOS technology ~Jmodesof operation are Programmable Interval TimerSystem Interface Block DiagramPreliminary Functional Description System InterfaceProgrammable DMA Controller System Application System InterfaceDack 2 CS-------It LJJ Intel CPU GroupROMs RAMs Peripheral Coming SoonIt-j ~~~1735~ Lead CerDIP Dual IN-LINE Package D \.--.J.. ~~~l·34o~ Lead Plastic Dual IN-LINE Package PSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Summary of Processor Instructions By Alphabetical Order Instruction SETMicrocomputer System Users Registration Card Microcomputer Systems Bowers Avenue Santa Clara, CA Intel CorporationInter
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8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.
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