Intel 8080 Program Counter Jumps, Subroutines and the Stack, Instruction Register and Decoder

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registers eliminates the need to "shuffle" intermediate re- sults back and forth between memory and the accumulator, thus improving processing speed and efficiency.

Program Counter (Jumps, Subroutines and the Stack):

The instructions that make up a program are stored in the system's memory. The central processor references the contents of memory, in order to determine what action is appropriate. This means that the processor must know which location contains the next instruction.

Each of the locations in memory is numbered, to dis- tinguish it from all other locations in memory. The number which identifies a memory location is called its Address.

The processor maintains a counter which contains the address of the next program instruction. This register is called the Program Counter. The processor updates the pro- gram counter by adding "1" to the counter each time it fetches an instruction, so that the program counter is always current (pointing to the next instruction).

The programmer therefore stores his instructions in numerically adjacent addresses, so that the lower addresses contain the first instructions to be executed and the higher addresses contain later instructions. The only time the pro- grammer may violate this sequential rule is when an instruc- tion in one section of memory is a Jump instruction to another section of memory.

A jump instruction contains the address of the instruc- tion which is to follow it. The next instruction may be stored in any memory location, as long as the programmed jump specifies the correct address. During the execution of a jump instruction, the processor replaces the contents of its program counter with the address embodied in the Jump. Thus, the logical continuity of the program is ma.intained.

A special kind of program jump occurs when the stored program "Calls" a subroutine. In this kind of jump, the pro- cessor is required to "remember" the contents of the pro- gram counter at the time that the jump occurs. This enables the processor to resume execution of the main program when it is finished with the last instruction of the subroutine.

A Subroutine is a program within a program. Usually it is a general-purpose set of instructions that must be exe- cuted repeatedly in the course of a main program. Routines which calculate the square, the sine, or the logarithm of a program variable are good examples of functions often written as subroutines. Other examples might be programs designed for inputting or outputting data to a particular peripheral device.

The processor has a special way of handling sub- routines, in order to insure an orderly return to the main program. When the processor receives a Call instruction, it increments the Program Counter and stores the counter's contents in a reserved memory area known as the Stack. The Stack thus saves the address of the instruction to be executed after the subroutine is completed. Then the pro-

cessor loads the address specified in the Call into its Pro- gram Counter. The next instruction fetched will therefore be the first step of the subroutine.

The last instruction in any subroutine is a Return. Such an instruction need specify no address. When the processor fetches a Return instruction, it simply replaces the current contents of the Program Counter with the address on the top of the stack. This causes the processor to resume execu- tion of the calling program at the point immediately foUow- ing the original Call Instruction.

Subroutines are often Nested; that is, one subroutine will sometimes call a second subroutine. The second may call a third, and so on. This is perfectly acceptable, as long as the processor has enough capacity to store the necessary return addresses, and the logical provision for doing so. In other words, the maximum depth of nesting is determined by the depth of the stack itself. If the stack has space for storing three return addresses, then three levels of subrou- tines may be accommodated.

Processors have different ways of maintaining stacks. Some have facilities for the storage of return addresses built into the processor itself. Other processors use a reserved area of external memory as the stack and simply maintain a Pointer register which contains the address of the most recent stack entry. The external stack allows virtually un- limited subroutine nesting. In addition, if the processor pro- vides instructions that cause the contents of the accumulator and other general purpose registers to be "pushed" onto the stack or "popped" off the stack via the address stored in the stack pointer, multi-level interrupt processing (described later in this chapter) is possible. The status of the processor (i.e., the contents of all the registers) can be saved in the stack when an interrupt is accepted and then restored after the interrupt has been serviced. This ability to save the pro- cessor's status at any given time is possible even if an inter- rupt service routine, itself, is interrupted.

Instruction Register and Decoder:

Every computer has a Word Length that is characteris- tic of that machine. A computer's word length is usually determined by the size of its internal storage elements and interconnecting paths (referred to as Busses); for example, a computer whose registers and busses can store and trans- fer a bits of information has a characteristic word length of 8-bits and is referred to as an a-bit parallel processor. An eight-bit parallel processor generally finds it most efficient to deal with eight-bit binary fields, and the memory asso- ciated with such a processor is therefore organized to store eight bits in each addressable memory location. Data and instructions are stored in memory as eight-bit binary num- bers, or as numbers that are integral multiples of eight bits:

16bits, 24 bits, and so on. This characteristic eight-bit field is often referred to as a Byte.

Each operation that the processor can perform is identified by a unique byte of data known as an Instruction

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Contents Page Programmable Communication Interface Clock Generator for 8080ASystem Controller for 8080A Programmable Peripheral InterfaceContents Peri pherals 127Chapter Packaging Information Page Microcomputer Design Aids Advantages of Designing With MicrocomputersConventional System Programmed Logic Iii Applications Example1IIII~Iff1 Application Peripheral Devices EncounteredArchitecture of a CPU Typical Computer SystemAccumulator Program Counter Jumps, Subroutines and the Stack Instruction Register and DecoderArithmetic/Logic Unit ALU Control CircuitryAddress Registers Computer OperationsMemory Write Instruction FetchMemory Read Wait memory synchronizationPage Page INTE~ 8080 Photomicrograph With Pin DesignationsArchitecture of the 8080 CPU RegistersData Bus Buffer Arithmetic and Logic Unit ALUInstruction Register and Control Processor CycleMachine Cycle Identification State Transition Sequence HaltStatus Bit Definitions Status Word ChartStatus Information Definition CPU State Transition Diagram ?~~Rr\ ONE ,----- ~ State Associated Activities ~2. State DefinitionsRLrL- rL rL rL-rL- rLrL Interrupt Sequences¢2 -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL Halt Sequences Hold SequencesSTART-UP of the 8080 CPU 11. Halt Timing ~~~~t==p 001 STATUS6 Xram ~A~~~ll ~iA~~~11~iA~~ll,12 ~iA~~~11Value 111 000 001 010 011 100 101Typical Computer System Block Diagram Basic System OperationClock Generator and High Level Driver CPU Module Design8080 CPU Clock Generator Design~50ns ClK 0.......-..-.-----.. tf1A TTLHigh Level Driver Design Ststb !1 Page ROM Interface Interfacing the 8080 CPU to Memory and I/O DevicesRAM Interface Ill Isolated I/O InterfaceGeneral Theory Memory Mapped I/OInterface Example AddressingMemr to 13 Format 15 FormatInstruction and Data Formats 8080 Instruction SETByte Three I D7 Byte OneByte Two Addressing ModesDescription Format Symbols and AbbreviationsSymbols Meaning AllMOV r1, r2 Move Register Content of register r2 is moved to register r1Data Transfer Group Reg. indirect0 I R p 0 I R1 I 0 IArithmetic Group 0 I 0 oR 0 I 0 I D I DOCR M Decrement memory I ILogical Group Cycles States Addressing reg. indirect Flags Z,S,P ,CY,AC~11~ I 0 I 1 I 1 II 1 I 1 o I 1 I 1 I 1 1 10 I 0 I 0 I 1 I0 I 0 1 I Cycles States Flags noneBranch Group 000Ccondition addr I c c I c I 0 I 0 ISP ~ SP + Push rp Stack, I/O, and Machine Control GroupI 1 o 1 I R~ data Exchange stack top with Hand L~ SP + Cycles States Flags NoneInstruction SET Programmable Peripheral Interface 8224 8080A-1 8228 8080A-2 8080A M8080-A Page Schottky Bipolar PIN NamesOscillator Functional DescriptionGeneral Clock GeneratorPower-On Reset and Ready Flip-Flops Ststb Status StrobeCharacteristics Crystal RequirementsInput 8pFT42 T01 T02 T03 Toss Characteristics For tCY = 488.28 nsExample TORS tORH tOR FMAXPIN Configuration Block Diagram DbinGeneral BlockSignals Inta None ControlWaveforms Characteristics TA = Oc to 70C Vee = 5V ±5%TE~r Hlda to Read Status OutputsVTH GoUTStstb VCC=5V·-c GND ---. rIntel Silicon Gate MOS 8080 a ?oo .HVss Vee8080A Functional PIN Definition Capacitance CharacteristicsAbsolute Maximum RATINGS· IOl = 1.9mA on all outputsTiming Waveforms =..... -r-DATAIN~I~~~ ~~1 t CYCharacteristics Typical ~ Output Delay VS. a CapacitanceInstruction SET Typical InstructionsSilicon Gate MOS 8080.A Summary of Processor InstructionsInfel Silicon Gate MOS 8080A-1 Max Symbol Parameter TypUnit ~tOF.I Fft~l~-t TYPICAL!J. Output Delay VS. ~ Capacitance Infel Silicon Gate MOS 8080 A-2 J1A +10Cout VAOOR/OATA = VSS + O.45VSymbol Parameter Min Unit Test ConditionTypical ~ Output Delay VS. ~ Capacitance Min. Max. Unit Test ConditionPage Intel . Silicon Gate MOS M8080A Ence, arithmetic or logical, rotate Immediate mode or I/O instructionsRegister to regist~r, memory refer Interrupt instructionsSummary of Processor Instructions Llf17Silicon Gate MOS M8080A M8080A Functional PIN DefinitionIOL = 1.9mA on all outputs Absolute Maximum RatingsOperation Symbol Parameter Min. Max Unit Test Condition Silicon Gate MOS M8080A ~I~Page ROMs 8702A 8704 8708 8316A Page Silicon Gate MOS 8702A PIN Connections Operating CharacteristicsVoo ~10% Switching Characteristics1N= Vee = V ce\ \ Cs=o.~Characteristics for Programming Operation Operating Characteristics for Programming OperationSymbol Test SYMBOLTESTMIN. TYP. MAX. Unit ConditionsProgramming Operation of the 8702A Switching Characteristics for Programming OperationCS = OV Program OperationIII a Erasing Procedure Operation of the 8702A in Program ModeII. Programming of the 8702A Using Intel Microcomputers Programming Instructions for the 8702APage PIN Configurations Block Diagram PIN NamesIBB CommentIII VOH1Waveforms Symbol Parameter Typ. Max. Unit ConditionsTest Conditions Max UnitTpF Program Pulse Fall Time Parameter MinProgramming Current RnA Program Pulse Amplitude CS/WE = +12V Read/Program/Read Transitions+-------1 150 r PEEEf!1EJEZPlEzz$m=2!·m·· IccSilicon Gate MOS CS=O.O CommentMAX Unit Outa100 ns 7001 JJ.s ~~~H --4!~--~N-~-TA-AL-~-DU-T--~\200ns 500ns 300 ns Typical Characteristics Cs .. o.~ ~rSilicon Gate MOS Ilkc IlclIlpc ILOCoUT Conditions of Test for CharacteristicsCIN ~ ~ ~ Pppp Mask Option SpecificationsMarking Customer Number OateBlank ~ r ------ + -- t --- . L . ------ rJTitle Card 79-80PIN Configuration Block Diagram Intel Silicon Gate MOS ROM 8316AConditions of Test for 400CAPACITANCE2 TA = 25C, f = 1 MHz OU~TVALID WaveformsTypical D.C. Characteristics ILICO.N Gate MOS ROM 8316ASTO CustomerNumber Oate Mask Option Speci FicationsTitle Card COM~ANY NameRAMs Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOS10H = -150 p.A ~E~~=~utP~-t-·7~igh-~\/oltage-~------ ---- --i2-+---=~== ~== OC +----+Conditions of Test 00 ~Page PIN Configuration Logic Symbol Block Diagram Silicon Gate MOSICC1 Symbol Parameter Min. Typ.rIII ICC2Input Pulse Rise and Fall Times 20nsec Write 1~-tAW--.I-----I550 200 Timing Measurement Reference Level VoltPage Silicon Gate MOS Comment Power Dissipation Watt5V to +7V TA = OOC to +70C, Vee = 5V ±5% unless otherwise specifiedCapacitance T a = 25C, f = 1MHz 85o-·-···T+--~~~TL~~~EEt~~~P-.± Conditions of TestTypical A.C. Characteristics ~~~b~.JSilicon Gate MOS 8102A-4 TA = OC to +70 o e, Vcc = 5V ±5% unless otherwise specified 230 450300 Access Time VS LOAD·CAPACITANCE VIN Limits VS. TemperatureAccess Time VS Ambient Temperature Output Source Current VSFully Decoded Random Access BIT Dynamic Memory PIN Configuration Logic Symbol Block DiagramSilicon Gate MOS 81078·4 IOOAV2II.~ IMP~ri~~CERef = Read Cycle4000 Write CycleTypical Characteristics RWc 590 CD Symbol Parameter Min MaxNumbers in parentheses are for minimum cycle timing in ns Refresh Power DissipationStandby Power System Interfaces and FilteringTypical System BIT 256 x 4 Static Cmos RAM VOR ICC2VIH VOL VOH IcccrInput Pulse Rise and Fall Times 20nsec Timing Measurement Reference Level Volt~I----- t CW2 ------ . t PIN Configuration Logic Symbol Schottky BipolarConditions of Test Voo- --- ---TPower Supply Current Drain and Power Dissipation All driver outputs are in the state indicatedTypical System Dynamic Memory Refresh Controller Page 8212 8255 8251 Page PIN Configuration Logic Diagram EIGHT-BIT INPUT/OUTPUT PortFunctional Description OS2Are 3-state Basic Schematic SymbolsII. Gated Buffer 3·STATE Gated BufferInterrupt Instruction Port III. Bi-Directional Bus DriverIV. Interrupting Input Port BI-DIRECTIONAL BUS Driver8080 4 VI. Output Port With Hand-ShakingVII Status Latch OvJ \.. -4~Vee Viii SystemOUT SystemIX System DalN-t?!NrJ 1G~D L-~Characteristics Absolute Maximum Ratings·Typical Characteristics 052 ~OUT TpwTA = OC to + 75C Vee = +5V ± 5% Switching Characteristics12 pF Programmable Peripheral Interface ~~~lEI~S 1-- +SVRead/Write and Control Logic GeneralData Bus Buffer Basic Functional DescriptionGroup a and Group B Controls ResetPIN Configuration Ports A, B, and CDetailed Operational Description Mode SelectionSingle Bit Set/Reset Feature PA 7 ·pAoMode 0 Timing Operating Modes Mode 0 Basic Input/OutputInterrupt Control Functions Mode 0 Port Definition Chart Mode 0 Configurations119 Operating Modes Mode 1 Strobed Input/Output · / ,4Intr Interrupt Request Input Control Signal DefinitionIBF Input Buffer Full F/F Inte aOutput Control Signal Definition InteaOperating Modes Combinations of ModeBi-Directional Bus I/O Control Signal Definition Output OperationsMode 2 Control Word Mode 2 Bi-directional TimingMode 2 Combinations Mode 2 and Mode 0 OutputSource Current Capability on Port B and Port C Special Mode Combination ConsiderationsMode Definition Summary Table Reading Port C StatusKeyboard and Display Interface ApplicationsPrinter Interface Keyboard and Terminal Address InterfacePCO ~.LEFT/RIGHTSilicon Gate MOS Input High Voltage Val Output Low Voltage IOl = 1.6mA Characteristics TA = oc to 70C Vee = +5V ±5% vss = OVVil Input Low Voltage Time From STB = 0 To IBFMode 0 Basic Input Mode 1 Strobed Input Mode 2 Bi-directional Page Programmable Communication Interface ReadlWrite Control logic Reset ResetGeneral ClK ClockTxE Transmitter Empty Modem ControlDSR Data Set Ready DTR Data Termin·al ReadyRxRDY Receiver Ready Receiver BufferReceiver Control RxC Receiver ClockDetailed Operation Description Mode InstructionCommand Instruction ProgrammingAsynchronous Mode Receive Mode Instruction DefinitionAsynchronous Mode Transmission Data C~~RACTERMode Instruction Format, Synchronous Mode Synchronous Mode TransmissionSynchronous Mode Receive Synchronous Mode, Transmission FormatStatus Read Definition Command Instruction DefinitionCommand Instruction Format Status Read FormatSynchronous Interface to Terminal or Peripheral Device Asynchronous Serial Interface to CRT Terminal, DC-9600 BaudAsynchronous Interface to Telephone Lines Synchronous Interface to Telephone LinesIcc CapacitanceIOL TA = oc to 70C VCC = 5.0V ±5% Vss = OV Symbol Parameter Typ~AST BIT ,----1 RxDSRX ~4IlI RXD~Peripherals Page High Speed 1 OUT of 8 Binary Decoder Decoder Enable GateSystem Chip Select Decoder Using a very similar circuit to the I/O port decoder, an arPort Decoder 24K Memory InterfaceJJ,.--+-I----.....1 Logic Element Example\lJ IllSymbol VOL VOH Characteristics TA = OOC to +75C, Vee = 5.0V ±5%Typical Characteristics 8205Address or Enable to Output Delay VS. Ambient Temperature Switching Characteristics Conditions of Test Test LoadAddress or Enable to Output Delay VS. Load Capacitance Test Waveforms~ R PIN Configuration~ ~ Polled Method Interrupts in Microcomputer SystemsInterrupt Method Priority Encoder Current Status RegisterElR, ETlG, ENGl Control SignalsINTE, elK AO, A1, A2Level Controller Basic OperationI I Level ControllerCascading Los Operating CharacteristicsSymbol Parameter Limits Unit Conditions Min Typ.£1 Absolute Maximum RatingsCharacteristics and Waveforms TA = oc to +70C, vcc = +5V ±5% Schottky Bipolar +-......---- n cs 8216 8226Bi-Directional Driver Control Gating OlEN, CSMemory and 1/0 Interface to a Bi-directional Bus Applications of 8216/8226Large microcomputer systems it is often necessary to pro Input Load Current All Other Inputs VF =0.45 IcC Power Supply Current 120Input Load Current OlEN, CS VF =0.45 Input Leakage Current OlEN, CS VR =5.25VWaveforms OUTPage 8253 8257 8259 Page Programmable Interval Timer It uses nMOS technology ~Jmodesof operation areSystem Interface Block DiagramPreliminary Functional Description System InterfaceProgrammable DMA Controller Dack 2 System InterfaceSystem Application CS-------It LJJ Peripheral Coming Soon CPU GroupROMs RAMs Intel735~ ~~~1It-j Lead Plastic Dual IN-LINE Package P \.--.J.. ~~~l·34o~ Lead CerDIP Dual IN-LINE Package DSales and Marketing Offices Distributors Page Page Page Page Page Page Instruction SET Instruction SET Summary of Processor Instructions By Alphabetical OrderMicrocomputer System Users Registration Card Intel Corporation Microcomputer Systems Bowers Avenue Santa Clara, CAInter
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8080 specifications

The Intel 8085 and 8080 microprocessors were groundbreaking innovations in the world of computing, paving the way for future microprocessor development and personal computing.

The Intel 8080, introduced in 1974, was an 8-bit microprocessor that played a fundamental role in the early days of personal computing. With a 16-bit address bus, it had the capability to address 64 KB of memory. Running at clock speeds of 2 MHz, the 8080 was notable for its instruction set, which included 78 instructions and 246 opcodes. It supported a range of addressing modes including direct, indirect, and register addressing. The 8080 was compatible with a variety of peripherals and played a crucial role in the development of many early computers.

The microprocessor's architecture was based on a simple and efficient design, making it accessible for hobbyists and engineers alike. It included an 8-bit accumulator, which allowed for data manipulation and storage during processing. Additionally, the 8080 featured registers like the program counter and stack pointer, which facilitated program flow control and data management. Its ability to handle interrupts also made it suitable for multitasking applications.

The Intel 8085, introduced in 1976, was an enhancement of the 8080 microprocessor. It maintained a similar architecture but included several key improvements. Notably, the 8085 had a built-in clock oscillator, simplifying system design by eliminating the need for external clock circuitry. It also featured a 5-bit control signal for status line management, which allowed for more flexible interfacing with peripheral devices. The 8085 was capable of running at speeds of up to 3 MHz and had an extended instruction set with 74 instructions.

One of the standout features of the 8085 was its support for 5 extra instructions for stack manipulation and I/O operations, which optimized the programming process. Additionally, it supported serial communication, making it suitable for interfacing with external devices. Its 16-bit address bus retained the 64 KB memory addressing capability of its predecessor.

Both the 8080 and 8085 microprocessors laid the groundwork for more advanced microprocessors in the years that followed. They demonstrated the potential of integrated circuits in computing and influenced the design and architecture of subsequent Intel microprocessors. Their legacy endures in the way they revolutionized computing, making technology accessible to a broader audience, and their influence is still felt in the design and architecture of modern microprocessors today.