Intel 8080 manual Characteristics, Typical ~ Output Delay VS. a Capacitance

SILICON GATE MOS 8080A

A.C. CHARACTERISTICS (Continued)

TA = O°C to 70°C, Voo = +12V ± 5%, Vee = +5V ± 5%, Vss = -5V'±5%, V55 = OV, Unless Otherwise Noted

Symbol	Parameter	Min. Max.	Unit	Test Condition
t052	Data Setup Time to ~2 During DBIN	150	nsec
tOH (1)	Data Hold Time From ~2 During DBIN	[1 ]	nsec
tiE [2)	INTE Output Delay From ~2	200	nsec	CL'=50pf
tRS	READY Setup Time During ~2	120	nsec
tH5	HOLD Setup Time to ~2	140	nsec
tiS	INT Setup Time During ~2 (During cP1 in Halt Mode)	120	nsec
tH	Hold Time From ~2 (READY, INT, HOLD)	0	nsec
tFO	Delay to Float During Hold (Address and Data ~us)	120	nsec	-
tAW [2)	Address Stable Prior to WR	[5]	nsec
tow [2)	Output Data Stable Prior to WR	[6]	nsec
tWD[2]	Output Data Stable From WR	[7]	nsec
tWf\[2]	, Address Stable From WR	[7]	nsec	~ CL= 100pf: Address, Data
	.- -			CL=50pf: WR, HLDA, DBIN
tHF[2]	HLDA to Float Delay	[8]	nsec
tWF[2]	WR to Float Delay	[9]	nsec
tAH[2]	Address Hold Time After DBIN During HLDA	-20	nsec	--

NOTES:

1.Data input should be enabled with 'OBINstatus. No bus co~f1ict can then occur and data hold time is assured. tOH =50 ns or tOF, whichever is less.

2.Load Circuit.

							+5V
								2.1K
					8080A
				OUTPUT
			3.	tCY = t03 + tr~2 + t4>2 + tf~2 + t02 + t rit>1 ;> 480ns.
				TYPICAL ~ OUTPUT DELAY VS. A CAPACITANCE
0 7 .00	~			..lits	+20 r-----~-----r----~---__.
SYNC				>	+10
				«
				..J
				w
				C	0
OBIN				~
				:;)
				Q.
				~
				:;)	-10
				0
WR				<1
					-20
						-50	o
		t oc			-100			+50	+100
READY						.:1.	CAPACITANCE (pf)
						(CACTUAL - CSPEC )
WAIT			4. The following are relevant when interfacing the 8080A to devices having VIH = 3.3V:
	s-			a) Maximum output rise time from .8V to 3.3V = 100ns @ CL = SPEC.
HOLD				b) Output delay when measured to 3.0V == SPEC +60ns @ CL == SPEC.
		t oc ...-		c) If CL "* SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC.
			5.	tAW = 2 tCY -t03 -tr</>2 -140nsec.
HLDA			6. • tow =tCY -t03 -tr</>2 -l70nsec.
			7.	If not HLOA, two =tWA = t03 + t r</>2 +10ns. If HLOA, two =twA =twF.
			8.	tHF == t03 + t rc/>2 -50ns.
INT	~		9.	twF = t03 + t rc/>2 -10ns
		-t:1-	10. Data in must be stable for this period during OBIN ·T3. Both tOS1 and tOS2 must be satisfied.'
			11. Ready signal must be stable for this period during T 2 or TW. (Must be externally synchronized.)
			12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, TS
INTE	I			and TWH when in hold mode. (External synchronization is not required.)
			13.	Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be

recognized on the following instruction. (External synchronization is not required.)

14. This timing diagram, shows timing relationships only; it does not represent any specific machine cycle.

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