Intel 440GX manual Additional Guidelines, Minimizing Crosstalk, Practical Considerations

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Motherboard Layout and Routing Guidelines

2.3.6Additional Guidelines

2.3.6.1Minimizing Crosstalk

The following general rules will minimize the impact of crosstalk in the high speed GTL+ bus design:

•Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever possible. It may be necessary to use tighter spacings when routing between component pins.

•Avoid parallelism between signals on adjacent layers.

•Since GTL+ is a slow signal swing technology, it is important to isolate GTL+ signals from other signals by at least 0.025”. This will avoid coupling from signals that have larger voltage swings, such as 5V PCI.

•Select a board stack-up that minimizes the coupling between adjacent signals.

•Route GTL+ address, data and control signals in separate groups to minimize crosstalk between groups. The Pentium II processor uses a split transaction bus. In a given clock cycle, the address lines and corresponding control lines could be driven by a different agent than the data lines and their corresponding control lines.

2.3.6.2Practical Considerations

•Distribute VTT with a wide trace. A 0.050” minimum trace is recommended to minimize DC

losses. Route the VTT trace to all components on the system bus. Be sure to include decoupling capacitors. Guidelines for VTT distribution and decoupling are contained in Intel® Pentium® II Processor Power Distribution Guidelines.

•Place resistor divider pairs for VREF generation at the Intel® 440GX AGPset component. No VREF generation is needed at the processor(s). VREF is generated locally on the processor. Be sure to include decoupling capacitors. Guidelines for VREF distribution and decoupling are contained in P Intel® Pentium® II Processor Power Distribution Guidelines.

•There are six GTL+ signals that can be driven by more than one agent simultaneously. These signals may require extra attention during the layout and validation portions of the design. When a signal is asserted (driven low) by two agents on the same clock edge, the two falling wave fronts will meet at some point on the bus. This can create a large undershoot, followed by ringback which may violate the ringback specifications. This “wired-OR” situation should be simulated for the following signals: AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#.

•Lossless simulations can overstate the amount of ringing on GTL+ signals. Lossy simulations may help to make your results less pessimistic if ringing is a problem. Intel has found the

resistivity of copper in printed circuit board signal layers higher than the value of

0.662 Ω-mil2/in that has been published for annealed copper. Intel recommends using a value of 1.0 Ω-mil2/in for lossy simulations.

•Higher RTT values tend to increase the amount of ringback on the rising edge, while smaller values tend to increase the amount of ringback on the falling edge. It is not necessary to budget for RTT variation if your simulations comprehend the expected manufacturing variation.

•I/O Buffer models for the fast corner correspond to the minimum Tco. Slow corner buffers will be at least 500 ps slower. Therefore, it is only necessary to ensure that the minimum flight time is met when the network is driven by fast buffer models.

•I/O Buffer models for the slow corner correspond to the maximum Tco. Fast corner buffers will be at least 500 ps faster. It is only necessary to ensure that the maximum flight time is met when the network is driven by slow buffer models, as long as no ringback problems exist.

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Intel®440GX AGPset Design Guide

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Contents Intel 440GX AGPset Design GuideIntel440GX AGPset Design Guide Contents 6.4 Dimm Solution With FET SwitchesSystem Bus Clock Layout 6.3 6.5Thermals / Cooling Solutions 20.1 PIIX4E Power And Ground PinsISA and X-Bus Signals 82371EB PIIX4EVoltage Regulator Control Silicon IntelPentiumII Processor LAI IssueFET Switches4 DIMM/FET Design Intel440GX AGPset Platform Reference DesignSolution Space for Single Processor Design Based on Results Example ATX Placement for a UP Pentium II processorExample NLX Placement for a UP Intel Pentium II processor Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset 100 MHz TablesIntel Pentium II Processor and Intel 440GX AGPset Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsRevision History Date Revision DescriptionIntel440GX AGPset Design Guide Introduction Page Introduction About This Design GuideReferences Intel Pentium II Processor / Intel 440GX AGPset Overview Intel Pentium II ProcessorIntel 440GX AGPset VCRDram Interface System Bus InterfaceAccelerated Graphics Port Interface PCI Interface Wired for Management InitiativePCI-to-ISA/IDE Xcelerator PIIX4E System ClockingRemote Service Boot InstrumentationVoltage Definitions Power ManagementDesign Recommendations Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page Major Signal Sections 82443GX Top View BGA Quadrant AssignmentATX Form Factor Board Description NLX Form FactorFour Layer Board Stack-up Routing Guidelines Single Processor Design 1 GTL+ Description2 GTL+ Layout Recommendations Single Processor Network Topology and ConditionsRecommended Trace Lengths for Single Processor Design Single Processor Recommended Trace LengthsTrace Minimum Length Maximum Length Dual Processor Network Topology and Conditions Dual Processor SystemsSingle Processor Systems-Single-End Termination SET Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsMinimizing Crosstalk Additional GuidelinesPractical Considerations Design Methodology Performance Requirements 12. GTL+ Design ProcessSimulation Methodology Topology DefinitionPre-Layout Simulation Sensitivity Analysis Recommended 100 MHz System Flight Time SpecsPlacement & Layout Post-Layout SimulationValidation Crosstalk and the Multi-Bit Adjustment FactorFlight Time Measurement Signal Quality Measurement Edge Guideline @ Processor Edge Spec @ Processor CoreTiming Analysis Term DescriptionTiming Term Intel Pentium II Processor Intel 440GX AGPset 10. Recommended 100 MHz System Timing Parameters11. Recommended 100 MHz System Flight Time Specs Timing Term ValueAGP Layout and Routing Guidelines AGP Connector Up Option Layout GuidelinesConnector 12. Data and Associated Strobe13. Source Synchronous Motherboard Recommendations 14. Control Signal Line Length RecommendationsOn-board AGP Compliant Device Down Option Layout Guidelines WidthSpace Trace Line Length Line Length MatchingCompliant 82443GX Graphics Data Routing Device 16. Control Signal Line Length Recommendations15. Source Synchronous Motherboard Recommendations 1 100 MHz 82443GX Memory Array Considerations 82443GX Memory Subsystem Layout and Routing GuidelinesTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Register Matching the Reference PlanesAdding Additional Decoupling Capacitor Register Data Control ClockMemory Layout & Routing Guidelines Trace Width vs. Trace Spacing18. FET Switch DQ Route Example Switch 16212 Dimm Module82443GX 0.6 0.4 0.6 0.4 Dimm Module 82443GX Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs 25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs 3 4 Dimm Routing Guidelines no FETPCI Bus Routing Guidelines VCC3Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGASystem Bus Clock Layout Intel 440GX AGPset Clock Layout RecommendationsClock Routing Spacing 014 018 ClockNet Trace Length Min Max Cap PCI Clock LayoutSdram Clock Layout 440GX Ckbf DlkoAGP Clock Layout Net Trace Length Min Max Card TraceDesign Checklist Page Overview Pull-up and Pull-down Resistor ValuesSlot Connectivity Sheet 1 Intel Pentium II Processor ChecklistProcessor Pin Pin Connection Slot Connectivity Sheet 2 Slot Connectivity Sheet 3 GND & Power Pin DefinitionVtt VCC3 Reserved NC Vcc Intel Pentium II Processor Signals Intel Pentium II Processor ClocksDesign Checklist Slot 1 Decoupling Capacitors Uni-Processor UP Slot 1 ChecklistDual-Processor DP Slot 1 Checklist Voltage Regulator Module, VRMProcessor Frequency Select Intel 440GX AGPset Clocks1 CK100 100 MHz Clock Synthesizer SEL100/66#Ckbf Sdram 1 to 18 Clock Buffer Gcke and Dclkwr Connection1 82443GX Interface 82443GX Host BridgeGX Connectivity Sheet 1 GX Connectivity Sheet 2 GX Connectivity Sheet 3 2 82443GX GTL+ Bus Interface3 82443GX PCI Interface VTTA, Vttb4 82443GX AGP Interface Signal Description Register Pulled to ‘0’ Pulled to ‘1’Strapping Options Sdram Connections 82443GX Pins/Connection Dimm Pins Pin FunctionIntel 440GX AGPset Memory Interface Sdram ConnectivityDimm Solution With FET Switches Registered SdramPIIX4E Connections Signal Names Connection82371EB PIIX4E PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Cabling Signal ResistorIDE Routing Guidelines MotherboardPin32,34 Reset#PDD150 PDA20 IDEPIIX4E Power And Ground Pins PCI Bus SignalsPIIX4E PWR & GND 10. Non-PIIX4E PCI Signals ISA SignalsISA and X-Bus Signals 11. Non-PIIX4E ISA SignalsIDE Interface USB Interface12. Non-PIIX4E IDE Flash Design Considerations Flash DesignDual-Footprint Flash Design PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 13. Flash Vpp Recommendations Write ProtectionSystem and Test Signals Power Management SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic Manageability Devices 18.1 Max1617 Temperature Sensor18.2 LM79 Microprocessor System Hardware Monitor Pin Number Pin Name Resistor Value Comment 18.3 82558B LOM ChecklistRequired in both a and B stepping designs USB and Multi-processor Bios Software/BIOSWake On LAN WOL Header Mechanicals Thermals / Cooling SolutionsDesign Considerations Electricals Routing and Board Fabrication Layout ChecklistApplications and Add-in Hardware Design ConsiderationDebug Recommendations Page Logic Analyzer Interface LAI Slot 1 Test ToolsDebug/Simulation Tools In-Target Probe ITPBus Functional Model BFM Debug FeaturesIntel Pentium II Processor LAI Issue 4 I/O Buffer Models430 ohm 150 330 ohmKohm 150 ohmA20M# 150 330 ohm Debug Logic RecommendationsPICD0# 150 ohm PICD1# Debug Considerations Debug ProceduresDebug Layout Design ConsiderationsDebug Recommendations Third Party Vendors Page GTL+ Bus Slot 1 Terminator Cards Slot 1 ConnectorProcessors Supplier Contact PhoneVoltage Regulator Modules Voltage Regulator ModulesVoltage Regulator Control Silicon Voltage Regulator Control Silicon VendorsIntel 440GX AGPset Power Management ComponentsFET Switches4 DIMM/FET Design Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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