Intel 440GX manual Intel Pentium II Processor Clocks, Intel Pentium II Processor Signals

Page 65

Design Checklist

3.3.2Intel® Pentium® II Processor Clocks

•Include a circuit for the system bus clock to core frequency ratio to the processor. The ratio should be configurable as opposed to hard wired. The bus frequency select straps will be latched on the rising edge of CRESET#.

•CRESET# is used as the selection signal for muxing A20M#, IGNNE#, INTR, and NMI with the processor bus/core frequency selection jumpers. A ‘244 buffer maybe used as a mux. The outputs of the ‘244 device are fed to open collector buffers for voltage translation to the CPU. See the reference board schematics for specific implementation.

•PICCLK must be driven by a clock even if an I/O APIC is not being used. This clock can be as high as 33.3 MHz in a UP system. A DP system utilizing Intel’s I/O APIC (82093AA) has a maximum PICCLK frequency of 16.666 MHz.

3.3.3Intel® Pentium® II Processor Signals

•Dual termination (56 ohm) to Vtt of the GTL+ bus is required if the trace length restrictions of a SET (single-ended termination) environment cannot be met.

•THERMTRIP# must be pulled-up to Vcc2.5 (150 ohm to 10K ohm) if used by system logic. The signal may be wire-OR’ed and does not require an external gate. It may be left as NC if it is not used. See the Debug Recommendations for further information that may affect the resistor values.

•The FERR# output must be pulled up to Vcc2.5 (150 ohm to 10K ohm) and connected to the PIIX4E. The reference schematics uses 220 ohms. See the Debug Recommendations for further information that may affect these resistor values.

•PICD[1:0]# must have 150 ohm pull-ups to Vcc2.5 even if an I/O APIC is not being used. See the Debug Recommendations for further information that may affect these resistor values.

•All CMOS inputs should be pulled up to Vcc2.5 (150 ohm to 10K ohm). See the Debug Recommendations for further information that may affect these resistor values.

•Be sure the Slot 1 inputs are not being driven by 3.3V or 5V logic. Logic translation of 3.3V or 5V signals may be accomplished by using open-drain drivers pulled-up to Vcc2.5.

•The PWRGOOD input should be driven to the appropriate level from the active-high “AND”

of the Power-Good signals from the 5V, 3.3V and VccCORE supplies. The output of any logic used to drive PWRGOOD should be a Vcc2.5 level to the processor.

•No VREF should be generated for the Intel® Pentium® II processor. VREF is locally generated on the processor card.

•Vtt must have adequate bulk decoupling based on the reaction time of the regulator used to

generate Vtt. It must provide for a current ramp of up to 8A/uS while maintaining the voltage tolerance defined in the Intel® Pentium® II Processor datasheet.

•If an on-board voltage regulator is used instead of a VRM, VccCORE must have adequate bulk decoupling based on the reaction time of the regulator used to generate VccCORE. It must provide for a current ramp of up to 30A/uS while maintaining the VRM 8.2 DC-DC Converter Specification.

•The VID lines should have pull-up resistors ONLY if they are required by the Voltage Regulator Module or on board regulator that you have chosen. The pull-up voltage used should be to the regulator input voltage (5V or 12V). However, if 12V is used, a resistor divider should be utilized to lower the VID signal to CMOS/TTL levels. The VID signals may be used to detect the presence of a processor core. A pull-up is not required unless the VID signals are

Intel®440GX AGPset Design Guide

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Contents Design Guide Intel 440GX AGPsetIntel440GX AGPset Design Guide Contents System Bus Clock Layout 6.3 Dimm Solution With FET Switches6.4 6.5ISA and X-Bus Signals PIIX4E Power And Ground PinsThermals / Cooling Solutions 20.1 82371EB PIIX4EFET Switches4 DIMM/FET Design IntelPentiumII Processor LAI IssueVoltage Regulator Control Silicon Intel440GX AGPset Platform Reference DesignExample NLX Placement for a UP Intel Pentium II processor Example ATX Placement for a UP Pentium II processorSolution Space for Single Processor Design Based on Results Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset TablesIntel Pentium II Processor and Intel 440GX AGPset 100 MHz Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsDate Revision Description Revision HistoryIntel440GX AGPset Design Guide Introduction Page About This Design Guide IntroductionReferences Intel Pentium II Processor Intel Pentium II Processor / Intel 440GX AGPset OverviewVCR Intel 440GX AGPsetAccelerated Graphics Port Interface System Bus InterfaceDram Interface PCI-to-ISA/IDE Xcelerator PIIX4E Wired for Management InitiativePCI Interface System ClockingInstrumentation Remote Service BootDesign Recommendations Power ManagementVoltage Definitions Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page BGA Quadrant Assignment Major Signal Sections 82443GX Top ViewATX Form Factor NLX Form Factor Board DescriptionFour Layer Board Stack-up Routing Guidelines 2 GTL+ Layout Recommendations 1 GTL+ DescriptionSingle Processor Design Single Processor Network Topology and ConditionsTrace Minimum Length Maximum Length Single Processor Recommended Trace LengthsRecommended Trace Lengths for Single Processor Design Single Processor Systems-Single-End Termination SET Dual Processor SystemsDual Processor Network Topology and Conditions Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsPractical Considerations Additional GuidelinesMinimizing Crosstalk Design Methodology 12. GTL+ Design Process Performance RequirementsPre-Layout Simulation Sensitivity Analysis Topology DefinitionSimulation Methodology Recommended 100 MHz System Flight Time SpecsPost-Layout Simulation Placement & LayoutFlight Time Measurement Crosstalk and the Multi-Bit Adjustment FactorValidation Edge Guideline @ Processor Edge Spec @ Processor Core Signal Quality MeasurementTerm Description Timing Analysis11. Recommended 100 MHz System Flight Time Specs 10. Recommended 100 MHz System Timing ParametersTiming Term Intel Pentium II Processor Intel 440GX AGPset Timing Term ValueConnector AGP Connector Up Option Layout GuidelinesAGP Layout and Routing Guidelines 12. Data and Associated StrobeOn-board AGP Compliant Device Down Option Layout Guidelines 14. Control Signal Line Length Recommendations13. Source Synchronous Motherboard Recommendations WidthSpace Trace Line Length Line Length Matching15. Source Synchronous Motherboard Recommendations 16. Control Signal Line Length RecommendationsCompliant 82443GX Graphics Data Routing Device To 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs 82443GX Memory Subsystem Layout and Routing Guidelines1 100 MHz 82443GX Memory Array Considerations Adding Additional Decoupling Capacitor Matching the Reference PlanesRegister Register Data Control ClockTrace Width vs. Trace Spacing Memory Layout & Routing GuidelinesSwitch 16212 Dimm Module 18. FET Switch DQ Route Example82443GX Dimm Module 82443GX 0.6 0.4 0.6 0.4 Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 21. Motherboard Model SCASB#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs20. Motherboard Model SCASA#, 4 DIMMs 24. Motherboard Model MAA140, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs23. Motherboard Model WEB#, 4 DIMMs PCI Bus Routing Guidelines 3 4 Dimm Routing Guidelines no FET25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs VCC3Host Bridge Controller 492 BGA Decoupling Guidelines Intel 440GX AGPset PlatformClock Routing Spacing Intel 440GX AGPset Clock Layout RecommendationsSystem Bus Clock Layout 014 018 ClockSdram Clock Layout PCI Clock LayoutNet Trace Length Min Max Cap 440GX Ckbf DlkoNet Trace Length Min Max Card Trace AGP Clock LayoutDesign Checklist Page Pull-up and Pull-down Resistor Values OverviewProcessor Pin Pin Connection Intel Pentium II Processor ChecklistSlot Connectivity Sheet 1 Slot Connectivity Sheet 2 Vtt VCC3 Reserved NC Vcc GND & Power Pin DefinitionSlot Connectivity Sheet 3 Intel Pentium II Processor Clocks Intel Pentium II Processor SignalsDesign Checklist Dual-Processor DP Slot 1 Checklist Uni-Processor UP Slot 1 ChecklistSlot 1 Decoupling Capacitors Voltage Regulator Module, VRM1 CK100 100 MHz Clock Synthesizer Intel 440GX AGPset ClocksProcessor Frequency Select SEL100/66#Gcke and Dclkwr Connection Ckbf Sdram 1 to 18 Clock BufferGX Connectivity Sheet 1 82443GX Host Bridge1 82443GX Interface GX Connectivity Sheet 2 3 82443GX PCI Interface 2 82443GX GTL+ Bus InterfaceGX Connectivity Sheet 3 VTTA, VttbStrapping Options Signal Description Register Pulled to ‘0’ Pulled to ‘1’4 82443GX AGP Interface Intel 440GX AGPset Memory Interface 82443GX Pins/Connection Dimm Pins Pin FunctionSdram Connections Sdram ConnectivityRegistered Sdram Dimm Solution With FET Switches82371EB PIIX4E Signal Names ConnectionPIIX4E Connections PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 IDE Routing Guidelines Signal ResistorCabling MotherboardPDD150 PDA20 Reset#Pin32,34 IDEPIIX4E PWR & GND PCI Bus SignalsPIIX4E Power And Ground Pins ISA and X-Bus Signals ISA Signals10. Non-PIIX4E PCI Signals 11. Non-PIIX4E ISA Signals12. Non-PIIX4E IDE USB InterfaceIDE Interface Dual-Footprint Flash Design Flash DesignFlash Design Considerations PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 Write Protection 13. Flash Vpp RecommendationsPower Management Signals System and Test SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic 18.2 LM79 Microprocessor System Hardware Monitor 18.1 Max1617 Temperature SensorManageability Devices Required in both a and B stepping designs 18.3 82558B LOM ChecklistPin Number Pin Name Resistor Value Comment Wake On LAN WOL Header Software/BIOSUSB and Multi-processor Bios Design Considerations Thermals / Cooling SolutionsMechanicals Electricals Applications and Add-in Hardware Layout ChecklistRouting and Board Fabrication Design ConsiderationDebug Recommendations Page Debug/Simulation Tools Slot 1 Test ToolsLogic Analyzer Interface LAI In-Target Probe ITPIntel Pentium II Processor LAI Issue Debug FeaturesBus Functional Model BFM 4 I/O Buffer ModelsKohm 150 330 ohm430 ohm 150 ohmPICD0# 150 ohm PICD1# Debug Logic RecommendationsA20M# 150 330 ohm Debug Layout Debug ProceduresDebug Considerations Design ConsiderationsDebug Recommendations Third Party Vendors Page Processors Slot 1 ConnectorGTL+ Bus Slot 1 Terminator Cards Supplier Contact PhoneVoltage Regulator Control Silicon Voltage Regulator ModulesVoltage Regulator Modules Voltage Regulator Control Silicon VendorsFET Switches4 DIMM/FET Design Power Management ComponentsIntel 440GX AGPset Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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