Intel 440GX manual Ckbf Sdram 1 to 18 Clock Buffer, Gcke and Dclkwr Connection

Page 69

Design Checklist

3.4.2CKBF - SDRAM 1 to 18 Clock Buffer

•A 4.7K ohm pull-up to VCC3.3 on the OE pin is needed to enable the buffer.

•Note that DCLKRD pin has been changed to a no connect (NC). The DCLKRD functionality has been combined with DCLKWR. If desire to remove the trace going to DCLKRD pin, the capacitor value should be adjusted to compensate for the capacitance change.

•An I2C interface is provided which allows the BIOS to disable unused SDRAM clocks to reduce EMI and power consumption. It is recommended that the BIOS disable unused clocks.

•No series termination is required for the SDRAM clocks between the CKBF and the DIMMs.

•DCLKO from the 82443GX to the CKBF should have a 22 ohm series resistor placed at the 82443GX, and a 47 ohm series resistor placed at the CKBF. This has been shown in simulations to improve the signal integrity of this signal.

•Check with your clock vendor and the reference schematics for special layout and decoupling considerations. The reference schematics implement an LC filter on the supply pins to reduce noise.

3.4.3GCKE and DCLKWR Connection

•See the diagram below for implementation of the 16-bit flip-flop for CKE generation for 4 DIMMs.

•GCKE trace length from the 82443GX to the flip-flop is recommended to be 1” MIN to 4” MAX. CKE trace lengths from the flip-flop to the DIMMS is recommended to be 3”.

Figure 3-2. GCKE & DCLKWR Connections

D C L K W R NC (AB22)

G C K E

82443GX

G N D

C K B F

 

 

 

27pF

 

 

 

 

 

 

1 D 1

 

 

 

 

 

 

 

 

 

 

1 D 2

 

 

 

 

 

1 D 3

 

 

20pF

 

1 D 4

 

 

 

1 D 5

 

 

 

 

 

1 D 6

 

 

 

 

 

1 D 7

 

 

 

 

 

1 D 8

 

 

 

 

 

2 D 1

 

- Clock signals fed back into 82443GX and

2 D 2

 

2 D 3

 

D-FF must ‘T’-off with equal trace length

 

2 D 4

 

and as close as possible to the 82443GX and

 

2 D 5

 

D-FF.

 

 

 

2 D 6

 

- The capacitors must be placed close to

the

 

2 D 7

 

node where the clock signals are ‘T’-ed.

 

2 D 8

 

- The capacitor values are shown.

 

 

 

 

1EN

2EN C 1 C 2

7 4 L V C H 1 6 3 7 4

1 Q 1

C K E 7

1 Q 2

1D3, 1D4

1 Q 3

C K E 6

1 Q 4

1D5, 1D6

1 Q 5

C K E 5

1 Q 6

1D7, 1D8

1 Q 7

C K E 4

1 Q 8

2D1, 2D2

2 Q 1

C K E 3

2 Q 2

2D3, 2D4

2 Q 3

C K E 2

2 Q 4

2D5, 2D6

2 Q 5

C K E 1

2 Q 6

2D7, 2D8

2 Q 7

C K E 0

2 Q 8

 

 

v007

NOTES:

1.The above circuitry only applies to unbuffer DIMMS. GCKE needs to be disabled for register DIMMS.

2.Pin AB22 has been changed to a no connect (NC), The 82443GX does not have an internal connection for pin AB22. Existing designs connected DCLKWR & AB22 nets on the motherboard. Since the 82443GX does not have an internal connection for pin AB22, it will cause a slightly reduced load capacitance on the net. To avoid additional clock skew on existing designs, a discrete capacitor larger than the 20pF capacitor recommended may be required.

Intel®440GX AGPset Design Guide

3-9

Page 68 Page 70
Image 69
Page 68 Page 70
Contents Design Guide Intel 440GX AGPsetIntel440GX AGPset Design Guide Contents System Bus Clock Layout 6.3 Dimm Solution With FET Switches6.4 6.5ISA and X-Bus Signals PIIX4E Power And Ground PinsThermals / Cooling Solutions 20.1 82371EB PIIX4EFET Switches4 DIMM/FET Design IntelPentiumII Processor LAI IssueVoltage Regulator Control Silicon Intel440GX AGPset Platform Reference DesignExample NLX Placement for a UP Intel Pentium II processor Example ATX Placement for a UP Pentium II processorSolution Space for Single Processor Design Based on Results Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset TablesIntel Pentium II Processor and Intel 440GX AGPset 100 MHz Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsDate Revision Description Revision HistoryIntel440GX AGPset Design Guide Introduction Page About This Design Guide IntroductionReferences Intel Pentium II Processor Intel Pentium II Processor / Intel 440GX AGPset OverviewVCR Intel 440GX AGPsetSystem Bus Interface Dram InterfaceAccelerated Graphics Port Interface PCI-to-ISA/IDE Xcelerator PIIX4E Wired for Management InitiativePCI Interface System ClockingInstrumentation Remote Service BootDesign Recommendations Power ManagementVoltage Definitions Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page BGA Quadrant Assignment Major Signal Sections 82443GX Top ViewATX Form Factor NLX Form Factor Board DescriptionFour Layer Board Stack-up Routing Guidelines 2 GTL+ Layout Recommendations 1 GTL+ DescriptionSingle Processor Design Single Processor Network Topology and ConditionsSingle Processor Recommended Trace Lengths Recommended Trace Lengths for Single Processor DesignTrace Minimum Length Maximum Length Single Processor Systems-Single-End Termination SET Dual Processor SystemsDual Processor Network Topology and Conditions Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsAdditional Guidelines Minimizing CrosstalkPractical Considerations Design Methodology 12. GTL+ Design Process Performance RequirementsPre-Layout Simulation Sensitivity Analysis Topology DefinitionSimulation Methodology Recommended 100 MHz System Flight Time SpecsPost-Layout Simulation Placement & LayoutCrosstalk and the Multi-Bit Adjustment Factor ValidationFlight Time Measurement Edge Guideline @ Processor Edge Spec @ Processor Core Signal Quality MeasurementTerm Description Timing Analysis11. Recommended 100 MHz System Flight Time Specs 10. Recommended 100 MHz System Timing ParametersTiming Term Intel Pentium II Processor Intel 440GX AGPset Timing Term ValueConnector AGP Connector Up Option Layout GuidelinesAGP Layout and Routing Guidelines 12. Data and Associated StrobeOn-board AGP Compliant Device Down Option Layout Guidelines 14. Control Signal Line Length Recommendations13. Source Synchronous Motherboard Recommendations WidthSpace Trace Line Length Line Length Matching16. Control Signal Line Length Recommendations Compliant 82443GX Graphics Data Routing Device15. Source Synchronous Motherboard Recommendations 82443GX Memory Subsystem Layout and Routing Guidelines 1 100 MHz 82443GX Memory Array ConsiderationsTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Adding Additional Decoupling Capacitor Matching the Reference PlanesRegister Register Data Control ClockTrace Width vs. Trace Spacing Memory Layout & Routing GuidelinesSwitch 16212 Dimm Module 18. FET Switch DQ Route Example82443GX Dimm Module 82443GX 0.6 0.4 0.6 0.4 Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs PCI Bus Routing Guidelines 3 4 Dimm Routing Guidelines no FET25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs VCC3Host Bridge Controller 492 BGA Decoupling Guidelines Intel 440GX AGPset PlatformClock Routing Spacing Intel 440GX AGPset Clock Layout RecommendationsSystem Bus Clock Layout 014 018 ClockSdram Clock Layout PCI Clock LayoutNet Trace Length Min Max Cap 440GX Ckbf DlkoNet Trace Length Min Max Card Trace AGP Clock LayoutDesign Checklist Page Pull-up and Pull-down Resistor Values OverviewIntel Pentium II Processor Checklist Slot Connectivity Sheet 1Processor Pin Pin Connection Slot Connectivity Sheet 2 GND & Power Pin Definition Slot Connectivity Sheet 3Vtt VCC3 Reserved NC Vcc Intel Pentium II Processor Clocks Intel Pentium II Processor SignalsDesign Checklist Dual-Processor DP Slot 1 Checklist Uni-Processor UP Slot 1 ChecklistSlot 1 Decoupling Capacitors Voltage Regulator Module, VRM1 CK100 100 MHz Clock Synthesizer Intel 440GX AGPset ClocksProcessor Frequency Select SEL100/66#Gcke and Dclkwr Connection Ckbf Sdram 1 to 18 Clock Buffer82443GX Host Bridge 1 82443GX InterfaceGX Connectivity Sheet 1 GX Connectivity Sheet 2 3 82443GX PCI Interface 2 82443GX GTL+ Bus InterfaceGX Connectivity Sheet 3 VTTA, VttbSignal Description Register Pulled to ‘0’ Pulled to ‘1’ 4 82443GX AGP InterfaceStrapping Options Intel 440GX AGPset Memory Interface 82443GX Pins/Connection Dimm Pins Pin FunctionSdram Connections Sdram ConnectivityRegistered Sdram Dimm Solution With FET Switches82371EB PIIX4E Signal Names ConnectionPIIX4E Connections PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 IDE Routing Guidelines Signal ResistorCabling MotherboardPDD150 PDA20 Reset#Pin32,34 IDEPCI Bus Signals PIIX4E Power And Ground PinsPIIX4E PWR & GND ISA and X-Bus Signals ISA Signals10. Non-PIIX4E PCI Signals 11. Non-PIIX4E ISA SignalsUSB Interface IDE Interface12. Non-PIIX4E IDE Dual-Footprint Flash Design Flash DesignFlash Design Considerations PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 Write Protection 13. Flash Vpp RecommendationsPower Management Signals System and Test SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic 18.1 Max1617 Temperature Sensor Manageability Devices18.2 LM79 Microprocessor System Hardware Monitor 18.3 82558B LOM Checklist Pin Number Pin Name Resistor Value CommentRequired in both a and B stepping designs Software/BIOS USB and Multi-processor BiosWake On LAN WOL Header Thermals / Cooling Solutions MechanicalsDesign Considerations Electricals Applications and Add-in Hardware Layout ChecklistRouting and Board Fabrication Design ConsiderationDebug Recommendations Page Debug/Simulation Tools Slot 1 Test ToolsLogic Analyzer Interface LAI In-Target Probe ITPIntel Pentium II Processor LAI Issue Debug FeaturesBus Functional Model BFM 4 I/O Buffer ModelsKohm 150 330 ohm430 ohm 150 ohmDebug Logic Recommendations A20M# 150 330 ohmPICD0# 150 ohm PICD1# Debug Layout Debug ProceduresDebug Considerations Design ConsiderationsDebug Recommendations Third Party Vendors Page Processors Slot 1 ConnectorGTL+ Bus Slot 1 Terminator Cards Supplier Contact PhoneVoltage Regulator Control Silicon Voltage Regulator ModulesVoltage Regulator Modules Voltage Regulator Control Silicon VendorsFET Switches4 DIMM/FET Design Power Management ComponentsIntel 440GX AGPset Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
Top Page Image Contents