Intel 440GX manual XD70

Page 86

Design Checklist

Following are general layout guidelines for using the Intel’s boot block flash memories (28F001GX/28F002BC) in the system:

•If adding a switch on VPP for write protection, switch to GND instead of VCC.

•Connect the DU pin of the 2Mbit devices to GND if anticipating to use the Intel SmartVoltage boot block flash memory family in the future.

•Use A16 inversion for 1Mbit devices and A17 inversion for 2Mbit devices to differentiate between recovery and normal modes. For systems needing a 1Mb to 2Mb upgrade path, A16 can be used for both devices alleviating the need for a board redesign.

•Use a 0.01mf - 0.1mf ceramic capacitor connected between each Vcc and GND, and between its Vpp and GND. These high frequency, inherently low inductance capacitors should be placed as close as possible to the package leads.

Figure 3-6illustrates the recommended layout for using Intel’s flash devices in desktop designs.

Figure 3-6. nterfacing Intel’s Flash with PIIX4E in Desktop

 

 

 

 

XD[7:0]

 

+ 1 2 V

 

 

 

L S 2 4 5

 

 

 

 

 

 

 

 

 

 

 

 

 

A

B

 

 

1

 

 

SD[7:0]

 

 

J1

 

 

 

 

 

 

 

V p p

2

 

V c c

 

 

 

 

1Mbit/2Mbit

+ 1 2 V

X D I R #

D I R

 

 

3

 

 

 

 

Flash

0.01uf

 

 

 

 

 

 

1

 

 

X O E #

G

 

 

 

R P #

J2

 

 

PIIX4E

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

1Mbit uses SA16

 

 

 

3

 

 

 

2Mbit uses SA17

1

 

 

0.01uf

 

 

 

 

 

V c c

 

 

 

 

 

J3

S A 1 6 /

 

 

 

S A 1 6 /

 

 

 

 

 

 

 

 

2

S A 1 7

V c c

 

 

 

S A 1 7

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

M E M W #

 

 

 

 

 

 

 

 

 

 

W E #

 

 

 

 

 

 

 

 

 

 

 

 

M E M R #

 

 

 

O E #

D U

 

 

 

B I O S C S #

 

 

 

C E #

 

 

 

 

 

J3

 

 

 

 

Mode

J1

J2

 

Mode

POS

 

 

 

 

 

Program

1-2

1-2

 

Recovery

 

1-2

 

 

 

 

 

 

PnP

1-2

2-3

 

Normal

 

2-3

 

 

 

 

 

 

Non-PnP

2-3

x

 

 

 

 

 

 

Simplified 2.7/3V/5V Design Considerations

Following are general layout guidelines for the Intel’s SmartVoltage/Smart 5 boot block flash memory (2/4Mbit BV/B5) in 3V or 5V designs:

•Connect 2.7V, 3V or 5V to VCC and connect 5V or 12V to VPP (program/erase levels) for BV devices.

•Connect 5V only to VCC and connect 5V or 12V to VPP (program/erase levels) for B5 devices.

•If adding a switch on VPP for write protection, switch to GND instead of VCC.

•Connect WP# to VCC, GND, or a general purpose output GPO[x] control signal. This pin should not be left floating. WP# pin replaces a DU pin and is used in conjunction with the VPP and RP# pins, as detailed in the table below, to control write protection of the boot block.

Intel®440GX AGPset Design Guide

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Contents Intel 440GX AGPset Design GuideIntel440GX AGPset Design Guide Contents 6.4 Dimm Solution With FET SwitchesSystem Bus Clock Layout 6.3 6.5Thermals / Cooling Solutions 20.1 PIIX4E Power And Ground PinsISA and X-Bus Signals 82371EB PIIX4EVoltage Regulator Control Silicon IntelPentiumII Processor LAI IssueFET Switches4 DIMM/FET Design Intel440GX AGPset Platform Reference DesignSolution Space for Single Processor Design Based on Results Example ATX Placement for a UP Pentium II processorExample NLX Placement for a UP Intel Pentium II processor Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset 100 MHz TablesIntel Pentium II Processor and Intel 440GX AGPset Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsRevision History Date Revision DescriptionIntel440GX AGPset Design Guide Introduction Page Introduction About This Design GuideReferences Intel Pentium II Processor / Intel 440GX AGPset Overview Intel Pentium II ProcessorIntel 440GX AGPset VCRAccelerated Graphics Port Interface System Bus InterfaceDram Interface PCI Interface Wired for Management InitiativePCI-to-ISA/IDE Xcelerator PIIX4E System ClockingRemote Service Boot InstrumentationVoltage Definitions Power ManagementDesign Recommendations Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page Major Signal Sections 82443GX Top View BGA Quadrant AssignmentATX Form Factor Board Description NLX Form FactorFour Layer Board Stack-up Routing Guidelines Single Processor Design 1 GTL+ Description2 GTL+ Layout Recommendations Single Processor Network Topology and ConditionsTrace Minimum Length Maximum Length Single Processor Recommended Trace LengthsRecommended Trace Lengths for Single Processor Design Dual Processor Network Topology and Conditions Dual Processor SystemsSingle Processor Systems-Single-End Termination SET Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsPractical Considerations Additional GuidelinesMinimizing Crosstalk Design Methodology Performance Requirements 12. GTL+ Design ProcessSimulation Methodology Topology DefinitionPre-Layout Simulation Sensitivity Analysis Recommended 100 MHz System Flight Time SpecsPlacement & Layout Post-Layout SimulationFlight Time Measurement Crosstalk and the Multi-Bit Adjustment FactorValidation Signal Quality Measurement Edge Guideline @ Processor Edge Spec @ Processor CoreTiming Analysis Term DescriptionTiming Term Intel Pentium II Processor Intel 440GX AGPset 10. Recommended 100 MHz System Timing Parameters11. Recommended 100 MHz System Flight Time Specs Timing Term ValueAGP Layout and Routing Guidelines AGP Connector Up Option Layout GuidelinesConnector 12. Data and Associated Strobe13. Source Synchronous Motherboard Recommendations 14. Control Signal Line Length RecommendationsOn-board AGP Compliant Device Down Option Layout Guidelines WidthSpace Trace Line Length Line Length Matching15. Source Synchronous Motherboard Recommendations 16. Control Signal Line Length RecommendationsCompliant 82443GX Graphics Data Routing Device To 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs 82443GX Memory Subsystem Layout and Routing Guidelines1 100 MHz 82443GX Memory Array Considerations Register Matching the Reference PlanesAdding Additional Decoupling Capacitor Register Data Control ClockMemory Layout & Routing Guidelines Trace Width vs. Trace Spacing18. FET Switch DQ Route Example Switch 16212 Dimm Module82443GX 0.6 0.4 0.6 0.4 Dimm Module 82443GX Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 21. Motherboard Model SCASB#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs20. Motherboard Model SCASA#, 4 DIMMs 24. Motherboard Model MAA140, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs23. Motherboard Model WEB#, 4 DIMMs 25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs 3 4 Dimm Routing Guidelines no FETPCI Bus Routing Guidelines VCC3Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGASystem Bus Clock Layout Intel 440GX AGPset Clock Layout RecommendationsClock Routing Spacing 014 018 ClockNet Trace Length Min Max Cap PCI Clock LayoutSdram Clock Layout 440GX Ckbf DlkoAGP Clock Layout Net Trace Length Min Max Card TraceDesign Checklist Page Overview Pull-up and Pull-down Resistor ValuesProcessor Pin Pin Connection Intel Pentium II Processor ChecklistSlot Connectivity Sheet 1 Slot Connectivity Sheet 2 Vtt VCC3 Reserved NC Vcc GND & Power Pin DefinitionSlot Connectivity Sheet 3 Intel Pentium II Processor Signals Intel Pentium II Processor ClocksDesign Checklist Slot 1 Decoupling Capacitors Uni-Processor UP Slot 1 ChecklistDual-Processor DP Slot 1 Checklist Voltage Regulator Module, VRMProcessor Frequency Select Intel 440GX AGPset Clocks1 CK100 100 MHz Clock Synthesizer SEL100/66#Ckbf Sdram 1 to 18 Clock Buffer Gcke and Dclkwr ConnectionGX Connectivity Sheet 1 82443GX Host Bridge1 82443GX Interface GX Connectivity Sheet 2 GX Connectivity Sheet 3 2 82443GX GTL+ Bus Interface3 82443GX PCI Interface VTTA, VttbStrapping Options Signal Description Register Pulled to ‘0’ Pulled to ‘1’4 82443GX AGP Interface Sdram Connections 82443GX Pins/Connection Dimm Pins Pin FunctionIntel 440GX AGPset Memory Interface Sdram ConnectivityDimm Solution With FET Switches Registered SdramPIIX4E Connections Signal Names Connection82371EB PIIX4E PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Cabling Signal ResistorIDE Routing Guidelines MotherboardPin32,34 Reset#PDD150 PDA20 IDEPIIX4E PWR & GND PCI Bus SignalsPIIX4E Power And Ground Pins 10. Non-PIIX4E PCI Signals ISA SignalsISA and X-Bus Signals 11. Non-PIIX4E ISA Signals12. Non-PIIX4E IDE USB InterfaceIDE Interface Flash Design Considerations Flash DesignDual-Footprint Flash Design PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 13. Flash Vpp Recommendations Write ProtectionSystem and Test Signals Power Management SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic 18.2 LM79 Microprocessor System Hardware Monitor 18.1 Max1617 Temperature SensorManageability Devices Required in both a and B stepping designs 18.3 82558B LOM ChecklistPin Number Pin Name Resistor Value Comment Wake On LAN WOL Header Software/BIOSUSB and Multi-processor Bios Design Considerations Thermals / Cooling SolutionsMechanicals Electricals Routing and Board Fabrication Layout ChecklistApplications and Add-in Hardware Design ConsiderationDebug Recommendations Page Logic Analyzer Interface LAI Slot 1 Test ToolsDebug/Simulation Tools In-Target Probe ITPBus Functional Model BFM Debug FeaturesIntel Pentium II Processor LAI Issue 4 I/O Buffer Models430 ohm 150 330 ohmKohm 150 ohmPICD0# 150 ohm PICD1# Debug Logic RecommendationsA20M# 150 330 ohm Debug Considerations Debug ProceduresDebug Layout Design ConsiderationsDebug Recommendations Third Party Vendors Page GTL+ Bus Slot 1 Terminator Cards Slot 1 ConnectorProcessors Supplier Contact PhoneVoltage Regulator Modules Voltage Regulator ModulesVoltage Regulator Control Silicon Voltage Regulator Control Silicon VendorsIntel 440GX AGPset Power Management ComponentsFET Switches4 DIMM/FET Design Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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