Intel Optimal Layout and Routing Guidelines for 440GX Network Cables

Motherboard Layout and Routing Guidelines

2.9.6Intel® 440GX AGPset Clock Layout Recommendations

2.9.6.1Clock Routing Spacing

A Intel® Pentium® II processor / Intel® 440GX AGPset platform requires a clock synthesizer for supplying 100 MHz system bus clocks, PCI clocks, APIC clocks, and 14 MHz clocks. These clocks are supplied by a CK100 clock synthesizer as defined by the CK97 clock/driver specification. The 100 MHz SDRAM DIMM clocks are generated from an I2C controlled clock buffer (CKBF) which produces 18 DIMM clock outputs from a single DCLK output provided by the 82443GX.

To minimize the impact of crosstalk, a minimum of 0.014” spacing should be maintained between the clock traces and other traces. A minimum spacing of 0.018” is recommended for serpentines.

Figure 2-30. Clock Trace Spacing Guidelines

0.014”

0.018”

Clock

2.9.6.2System Bus Clock Layout

System bus clock nets should be routed as point-to-point connections with a 22 Ohm series resistor that is to be placed as close to the output pins on the clock driver as possible (<0.5”).

In a UP system, clock skew between the 82443GX and the processor can be reduced by tying the clock driver pins together at the clock chip and driving the processor and 82443GX from this net with a 10 Ohm resistor at the driver for each. Trace lengths still match the specs defined below.

Layout guidelines: Match trace lengths to the longest trace.

Net	Trace length	min	max	Substrate
Clock chip - Processor	H	1.0”	9.0”	3.25”
Clock chip - 82443GX	H + 3.25”	1.0”	12.0”	NA
Clock chip - ITP	H + 4.00”	1.0”	13.0”	NA

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